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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16401-2E
32-bit RISC Microcontroller
CMOS
FR50 Family MB91360G Series
MB91FV360GA/F361GA/F362GA
s DESCRIPTION
The Fujitsu MB91360G series is a standard microcontroller containing a wide range of I/O peripherals and bus control functions. The MB91360G series features a 32-bit RISC CPU (FR50 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. The MB91360G series also contains up to 4 Kbyte instruction cache memory and other internal memories to improve the execution speed of the CPU.
s FEATURES
* Execution time : down to 15.6 ns (64 MHz) * FR50 series CPU : RISC architecture The CPU has a general-purpose register architecture with improved numeric implementation whereby a wide range of delayed branch instructions reduces losses in execution time due to pipeline breaks. Bit manipulation instructions and memory access instructions have been enhanced resulting in improved code efficiency and execution speed for control implementation. * A five-stage pipeline structure provides high-speed processing (one instruction per cycle) * 32-bit linear address space : 4 Gbytes * Fixed 16-bit instruction size (basic instructions) * High-speed multiplication/step division * High-speed interrupt processing (6 cycles) * General-purpose registers : 16 x 32 bits (Continued)
s PACKAGE
401-pin Ceramics PGA 208-pin plastic QFP
(PGA-401C-A02)
(FPT-208P-M04)
MB91360G Series
(Continued) * External bus interface unit with a wide range of functions Divides the external memory space into a maximum of eight areas. Chip select signal setting, data bus width selection (8, 16, 32-bit) , and area size can be specified for each area. * Address bus up to 32 bit wide * Programmable auto-wait function * Internal instruction cache The MB91360G series contains up to 4-Kbyte instruction cache to improve the execution speed of external programs. * Two-way set associative caching * DMAC Direct memory access (DMA) can be used to perform various types of data transfer without going via the CPU. This improves system performance. * Eight channels (including up to 3 external channels) * Three transfer modes supported : single/block, burst, continuous transfer * Power consumption control mechanisms The MB91360G series contains a number of functions for controlling the operating clock to reduce power consumption. * Software control : Sleep and stop/real time clock functions * Hardware control : Hardware standby function * Gear (divider) function : The CPU and peripheral clock frequencies can be set independently. * Contains a range of peripheral functions * UART, U-timer * Real Time Clock (with optional subclock operation and subclock calibration module) * Stepper Motor Control * Sound Generator * Serial IO (SIO) , SIO-Prescaler * Power Down Reset * Alarm Comparator * IO-Timer * I2C Interface * 10 Bit D/A Converter * CAN Interface * 10-bit A/D converter * 16-bit reload timer * 16-bit PWM timer * Watchdog timer * Bit search module * Interrupt controller * External interrupt inputs * I/O port function * Interrupt levels "16 maskable interrupt levels" * Other * Power supply voltage * 5 V power supply used, the internal regulator creates internal supply of 3.3 V * Package : MB91FV360GA uses a PGA401 package, MB91F361GA and MB91F362GA are delivered in a QFP208 package.
2
MB91360G Series
s PRODUCT LINEUP
Resource Channels Memory Size Cache/Instruction RAM D-bus RAM F-bus RAM Flash/ROM Boot ROM CAN Stepper Motor Control Sound Generator PPG Input Capture Output Compare Free Running Timer D/A Converter A/D Converter I2C 100 kHz I2C 400 kHz Alarm Comparator SIO/SIO prescaler UART/U-Timer 16-bit Reload Timer Ext. Interrupt Non maskable Interrupt Real Time Clock 32 kHz subclock option for RTC subclock calibration LED port Power down Reset Bit search Module Watchdog timer Ext. Address Bus Ext. Data Bus Ext. DMA Max. operating frequency MB91FV360GA 4 KB / 4 KB 16 KB 16 KB 512 KB on F-bus 2 KB 4 ch 4 ch 1 ch 8 ch 4 ch 4 ch 2 ch 2 ch 16 ch 1 ch 1 ch 2 ch 3 ch 6 ch 8 ch 1 1 yes yes 8 bit 1 1 1 32 bit 32 bit 3 ch 64 MHz MB91F361GA 1 KB / 1 KB 12 KB 4 KB 512 KB on ext. bus 2 KB 3 ch 4 ch 1 ch 8 ch 4 ch 4 ch 2 ch 2 ch 16 ch 1 ch 1 ch 2 ch 3 ch 6 ch 8 ch 1 no no 8 bit 1 1 1 21 bit 32 bit 1 ch 64 MHz MB91F362GA - / 4 KB 12 KB 4 KB 512 KB on F-bus 2 KB 3 ch 4 ch 1 ch 8 ch 4 ch 4 ch 2 ch 2 ch 16 ch 1 ch 1 ch 2 ch 3 ch 6 ch 8 ch 1 no no 8 bit 1 1 1 21 bit 32 bit 1 ch 64 MHz
3
MB91360G Series
s PIN ASSIGNMENTS
* MB91FV360GA (BOTTOM VIEW)
23 69 119 174 230 173 118 68 22 67 21 66 20 65 19 64 18 63 17 62 16 61 15 60 14 59 13 58 12 57 120 70 121 24 71 122 25 72 123 26 73 124 27 74 125 28 75 126 29 76 127 30 77 128 31 78 129 32 79 130 33 80 131 187 244 188 132 81 34 82 35 83 36 84 37 85 38 86 39 87 40 88 41 89 42 90 43 91 44 92
175
176
177
178
179
180
181
182
183
184
185
186
231
232
233
234
235
236
237
238
239
240
241
242
243
284
285
286
287
288
289
290
291
292
293
294
295
296
297
229
334
335
336
337
338
339
340
341
342
343
344
345
346
245
172 117
283
380
381
382
383
384
385
386
387
388
389
390
391
298
189 133
228
333 379
347 392
246
171 116
282
299
190 134
227
332 378
348 393
247
170 115
281
300
191 135
226
331 377
349 394
248
169 114
280
301
192 136
225
330 376
350 395
249
168 113
279
302
193 137
224
329 375
351 396
250
167 112
278
303
194 138
223
328 374
352 397
251
166 111
277
304
195 139
222
327 373
353 398
252
165 110
276
305
196 140
221
326 372
354 399
253
164 109
275
306
197 141
220
325 371
355 400
254
163 108
274
307
198 142
219
324 370
356 401
255
162 107
273
308
199 143
218
323 369 368 367 366 365 364 363 362 361 360 359
357 358
256
161 106
272
309
200 144
217
322
321
320
319
318
317
316
315
314
313
312
311
310
257
160
271
270
269
268
267
266
265
264
263
262
261
260
259
258
201
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202 145 INDEX
159
158
157
156
155
154
153 99 51 7 6
152 98 50 5
151 97 49 4
150 96 48 3
149 95 47 2
148 94 46 1
147 93 45
146
105 56
104 55 11
103 54 10
102 53 9
101 52 8
100
(PGA-401C-A02) 4
MB91360G Series
* MB91F361GA/F362GA (TOP VIEW)
UART CAN PPG SIO I2C Sound XTAL + PLL Mode OCU
156 157
SOT2 VSS VCC3C VDD HVSS PWM1P0 PWM1M0 PWM2P0 PWM2M0 HVDD PWM1P1 PWM1M1 PWM2P1 PWM2M1 HVSS PWM1P2 PWM1M2 PWM2P2 PWM2M2 HVDD PWM1P3 PWM1M3 PWM2P3 PWM2M3 HVSS VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 VDD VSS D15 D16 D17 D18 D19 D20 D21 D22 D23
SIN2 SOT1 SIN1 SOT0 SIN0 RX2 TX2 RX1 TX1 RX0 TX0 VSS VDD OCPA7 OCPA6 OCPA5 OCPA4 OCPA3 OCPA2 OCPA1 OCPA0 SCK3 SOT3 SIN3 SCK4 SIN4 SOT4 SCL SDA SGA SGO VCI CPO VSS X1A X0A X1 X0 VDD SELCLK MONCLK INIT HST MD2 MD1 MD0 VSS OUT3 OUT2 OUT1 OUT0 IN3
1
D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VDD VSS A16 A17 A18 A19 A20 CS4 CS5 CS6 RDY BGRNT BRQ RD WR0 WR1 WR2 WR3 AS ALE CLK AH/BOOT CS0 CS1 CS2 CS3 VDD VSS
208

,,,,,, ,,,,,,,,,
PQ [5:0] PP [5:0] PO [7:0] PN [5:0] PM [3:0] PR [7:0]
SMC
PJ [7:0]
PK [7:0]
PS [7:0]
P0 [7:0]
PI [6:0]
PH [7:0]
P1 [7:0]
PB [2:0]
INDEX P2 [7:0]
PG [7:0]
P3 [7:0]
P4 [7:0]
P5 [7:0]
P6 [4:0] P7 [4:6]
P8 [7:0]
P9 [7:0]
53 52
ext. Bus Data
ext. Bus Address
Chip Select
ext. Bus Control
Chip Select
(FPT-208P-M04)
ADC
DMA
ADC
DAC
LED
ext. Int.
,,,
PL [7:0]
105 104
IN2 IN1 IN0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 VSS VDD LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 LTEST CPUTEST TEST ATG VDD VSS ALARM DA1 DA0 AVSS AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVRH AVCC DEOP0 DACK0 DREQ0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8

ICU
5
MB91360G Series
s PIN DESCRIPTIONS
Pin No. QFP208 9 10 11 12 26 25 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 Pin No. PGA401 202 310 201 357 358 401 257 144 309 256 200 356 308 92 400 44 255 143 199 307 355 91 142 254 399 43 198 141 90 197 306 42 253 A17 A18 A19 VSS A20 A21 A22 A23 A24 A25 A26 DREQ2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P70 P71 P72 P73 Pin Name A0 A1 A2 A3 VSS VDD A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General Purpose IO Port Circuit Type FV360GA Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q not connected Q Q Q Q Q Q Q Q Q Q A Q Q Q Q Ext. Bus Address Bit 17 Ext. Bus Address Bit 18 Ext. Bus Address Bit 19 Ext. Bus Address Bit 20 Ext. Bus Address Bit 21 Ext. Bus Address Bit 22 Ext. Bus Address Bit 23 Ext. Bus Address Bit 24 Ext. Bus Address Bit 25 Ext. Bus Address Bit 26 DMA Request 2 F361GA F362GA Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Function Ext. Bus Address Bit 0 Ext. Bus Address Bit 1 Ext. Bus Address Bit 2 Ext. Bus Address Bit 3 Ext. Bus Address Bit 4 Ext. Bus Address Bit 5 Ext. Bus Address Bit 6 Ext. Bus Address Bit 7 Ext. Bus Address Bit 8 Ext. Bus Address Bit 9 Ext. Bus Address Bit 10 Ext. Bus Address Bit 11 Ext. Bus Address Bit 12 Ext. Bus Address Bit 13 Ext. Bus Address Bit 14 Ext. Bus Address Bit 15 Ext. Bus Address Bit 16
(Continued)
6
MB91360G Series
(Continued) Pin No.
QFP208 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 52 48 49 50 53 54 55 56 57 58 51
Pin No. PGA401 140 398 354 196 89 41 305 139 88 40 304 353 39 252 251 87 38 397 194 195 137 352 250 351 138 37 86 136 303 302 36 396 350 CLK AH/BOOT CS0 VSS CS1 CS2 CS3 AN8 AN9 AN10 AN11 AN12 AN13 VSS VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name CS4 VSS VDD CS5 CS6 CS7 RDY BGRNT BRQ RD WR0 VSS WR1 WR2 WR3 AS ALE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
General Purpose IO Port P74 P75 P76 P77 P81 P82 P90 P91
Circuit Type FV360GA A A A A S A A S S S S S A A not connected F361GA F362GA A A A S A A S S S S S A A Function Chip Select 4 Chip Select 5 Chip Select 6 Chip Select 7 (CANs) Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control Ext. Bus Control (Ext. Bus Control, not yet implemented) Ext. Bus Clk Test Signal/Boot Signal Chip select 0 Chip Select 1 Chip Select 2 Chip Select 3 ADC Input 8 ADC Input 9 ADC Input 10 ADC Input 11 ADC Input 12 ADC Input 13
P93 P94 P95 P96 P97 PG0 PG1 PG2 PG3 PG4 PG5
A A A A A A B B B B B B
A A A A A A B B B B B B
(Continued)
7
MB91360G Series
(Continued) Pin No.
QFP208 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Pin No. PGA401 85 249 193 135 84 301 192 191 395 35 349 83 300 248 393 82 134 34 394 190 247 81 133 299 348 246 189 132 392 347 298 245 188 297 AN1 AN2 AN3 VSS AN4 AN5 AN6 AN7 AVRL AVSS DA0 DA1 ALARM VSS VDD ATG TEST CPUTEST LTEST I/O I/O I/O I/O I/O I/O I/O O O I I/O I I I Pin Name AN14 AN15 DREQ0 DACK0 DEOP0 DREQ1 DACK1 DEOP1 VSS DACK2 DEOP2 AVCC AVRH AN0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
General Purpose IO Port PG6 PG7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PI3
Circuit Type FV360GA B B A A A A A A A A R B not connected B B B B B B B R C C D A E E E B B B B B B B C C D A E E E ADC Input 1 ADC Input 2 ADC Input 3 ADC Input 4 ADC Input 5 ADC Input 6 ADC Input 7 Analog Reference Low Analog VSS DAC Output DAC Output Alarm Comparator Input ADC Trigger Input Test Input Test Input Test Input (Continued) F361GA F362GA B B A A A R B Function ADC Input 14 ADC Input 15 DMA Request 0 DMA Acknowledge 0 DMA EOP 0 DMA Request 1 DMA Acknowledge 1 DMA EOP 1 DMA Acknowledge 2 DMA EOP 2 Analog VCC Analog Reference High ADC Input 0
8
MB91360G Series
(Continued) Pin No.
QFP208 84 85 86 87 88 89 90 91 94 95 96 93 97 98 99 100 101 92 102 103 104 110 105 106 107 108 109 111 112 113
Pin No. PGA401 244 346 187 345 391 390 243 131 296 242 186 344 295 80 389 33 241 130 185 294 343 79 129 240 388 32 184 128 78 183 293 31 239 127 LED3 LED4 LED5 LED6 LED7 INT0 INT1 INT2 VSS INT3 INT4 INT5 INT6 INT7 VDD IN0 IN1 IN2 VSS IN3 OUT0 OUT1 OUT2 OUT3 MD0 MD1 MD2 NMI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I LED0 LED1 LED2 VSS I/O I/O I/O Pin Name I/O
General Purpose IO Port
Circuit Type FV360GA F361GA F362GA J J J J J J J J A A A A A A A A A A A A A A A A T T T Function
not connected PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 J J J J J J J J A A A A A A A A A A A A A A A A T T T E not connected LED Port 3 LED Port 4 LED Port 5 LED Port 6 LED Port 7 Ext. Interrupt 0 Ext. Interrupt 1 Ext. Interrupt 2 Ext. Interrupt 3 Ext. Interrupt 4 Ext. Interrupt 5 Ext. Interrupt 6 Ext. Interrupt 7 ICU Input 0 ICU Input 1 ICU Input 2 ICU Input 3 OCU Output 0 OCU Output 1 OCU Output 2 OCU Output 3 Mode Pin 0 Mode Pin 1 Mode Pin 2 Non maskable Interrupt (Continued) 9 LED Port 0 LED Port 1 LED Port 2
MB91360G Series
(Continued) Pin No.
QFP208 114 115 116 117 118 119 120
Pin No. PGA401 387 342 182 77 30 292 126 76 29 291 341 28 238 237 75 27 386 180 181 124 340 236 339 125 26 74 123 290 289 25 385 338 73 235 HST RST INIT MONCLK SELCLK VDD X0 X1 VSS ICLK ICS0 ICS1 ICS2 ICD0 VDD ICD1 ICD2 ICD3 VSS BREAK TDT0 TDT1 TDT2 TDT3 TDT4 TDT5 TDT6 TDT7 VSS3 VDD3 TDT8 TDT9 I I I O I IO O O O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name VSS I/O
General Purpose IO Port
Circuit Type FV360GA E E U G F H H L G G G N N N N O W W W W W W W W W W F361GA F362GA E U G F H H Function Hardware Standby Reset Pin Initial Pin System Clock Output Clock Selection 4 MHz Oscillator Pin 4 MHz Oscillator Pin ICE CLK ICE Status ICE Status ICE Status ICE Data ICE Data ICE Data ICE Data ICE Break Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data (Continued)
not connected
10
MB91360G Series
(Continued) Pin No.
QFP208
Pin No. PGA401 179 122 72 288 178 177 384 24 337 71 287 234 382 70 121 23 383 176 233 69 120 286 336 232 175 119 381 335 285 231 174 284 230 334 TDT21 TDT22 TDT23 VSS3 TDT24 TDT25 TDT26 TDT27 TDT28 TDT29 TDT30 TDT31 TDT32 VSS3 VDD3 TDT33 TDT34 TDT35 TDT36 TDT37 TDT38 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name TDT10 TDT11 TDT12 TDT13 TDT14 TDT15 VSS3 TDT16 TDT17 TDT18 TDT19 TDT20 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
General Purpose IO Port
Circuit Type FV360GA W W W W W W W W W W W W W W W W W W W W W W W W W W W W W F361GA F362GA Function Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data (Continued) 11
not connected
MB91360G Series
(Continued) Pin No.
QFP208
Pin No. PGA401 173 333 380 379 229 118 283 228 172 332 282 68 378 22 227 117 171 281 331 67 116 226 377 21 170 115 66 169 280 20 225 114 376 330 TDT41 TDT42 TDT43 TDT44 TDT45 TDT46 TDT47 TDT48 VSS3 TDT49 TDT50 TDT51 TDT52 TDT53 VDD3 TDT54 TDT55 TDT56 VSS3 TDT57 TDT58 TDT59 TDT60 TDT61 TDT62 TDT63 TDT64 TDT65 VSS3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name TDT39 TDT40 VSS3 I/O I/O I/O
General Purpose IO Port
Circuit Type FV360GA W W W W W W W W W W W W W W W W W W W W W W W W W W W F361GA F362GA Function Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data Trace Data
not connected
not connected
(Continued)
12
MB91360G Series
(Continued) Pin No.
QFP208 126 127 128 129
Pin No. PGA401 168 65 19 279 113 64 18 278 329 17 224 223 63 16 375 166 167 111 328 222 327 112 15 62 110 277 276 14 374 326 61 221 165 109 Pin Name TDT66 TDT67 TDT68 TAD0 TAD1 TAD2 TAD3 TAD4 VSS3 TAD5 TAD6 TAD7 TAD8 TAD9 VDD3 TAD10 TAD11 TAD12 VSS3 TAD13 TAD14 TAD15 TWR TOE TCLK TCE1 TADSC EXRAM VSS VDD SGO SGA SDA SCL I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O I/O O O I I/O I/O I/O I/O
General Purpose IO Port PM0 PM1 PM2 PM3
Circuit Type FV360GA W W W X X X X X X X X X X X X X X X X X X W X X P A A Y Y F361GA F362GA A A Y Y Function Trace Data Trace Data Trace Data Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Address Trace Control Trace Control Trace Control Trace Control Trace Control Trace Control Sound Generator SGO Sound Generator SGA I2C SDA I2C SCL (Continued) 13
MB91360G Series
(Continued) Pin No.
QFP208 121
Pin No. PGA401 60 275 VDD I Pin Name I/O
General Purpose IO Port
Circuit Type FV360GA F361GA F362GA reserved should be connected to be VSS reserved should be left open reserved should be left open reserved should be connected to be VSS A A A A A A A A A A A A A A A A A A A A Function
not connected I 32 kHz Oscillator Pin
164
X0A
122 123 124
163 373 13 325
X1A VSS VDD CPO
O
not connected
I
32 kHz Oscillator Pin
125 130 131 132 133 134 135 136 137 138 139
59
VCI
not connected
274 220 371 58 108 12 372 162 219 57 107 273 324 218 161 106 370 323 272 SOT4 SIN4 SCK4 VSS VDD SIN3 SOT3 SCK3 VSS VDD OCPA0 OCPA1 OCPA2 VSS VDD OCPA3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PN0 PN1 PN2 PN3 PN4 PN5 PO0 PO1 PO2 PO3 VSS
not connected SIO Output SIO Input SIO Clock SIO Input SIO Output SIO Clock PPG Output PPG Output PPG Output PPG Output (Continued) not connected
14
MB91360G Series
(Continued) Pin No.
QFP208 140 141 144 142 143 146 145 147 148 149 150 151 152 153 154 155 156 160 157 159 158
Pin No. PGA401 217 160 271 216 322 159 321 369 368 215 105 270 214 158 320 269 56 367 11 213 104 157 268 319 55 103 212 366 10 156 102 54 155 267 VSS RX0 TX1 RX1 VSS VDD TX2 RX2 TX3 VSS VDD RX3 SIN0 SOT0 VSS VDD SIN1 SOT1 SIN2 VSS VDD SOT2 VCC3C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name OCPA4 OCPA5 VSS VDD OCPA6 OCPA7 TX0 VSS I/O I/O I/O I/O I/O I/O
General Purpose IO Port PO4 PO5 PO6 PO7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PQ0 PQ1 PQ2 PQ3 PQ4 PQ5
Circuit Type FV360GA A A A A Q Q Q Q Q Q Q Q A A A A A A C not connected not connected not connected Q Q Q Q Q A A A A A A C CAN 0 RX CAN 1 TX CAN 1 RX CAN 2 TX CAN 2 RX CAN 3 TX CAN 3 RX UART 0 Input UART 0 Output UART 1 Input UART 1 Output UART 2 Input VDD UART 2 Output Bypass Capacitor Pin F361GA F362GA A A A A Q Function PPG Output PPG Output PPG Output PPG Output CAN 0 TX
(Continued)
15
MB91360G Series
(Continued) Pin No.
QFP208 162 163 164 161 165 167 168 166 169 170 171 172 173 174 175 177 178 181 176 179 180 182 183 184 185
Pin No. PGA401 9 211 101 365 318 154 53 8 266 100 52 7 265 317 6 210 209 51 5 364 152 153 98 316 208 315 99 4 50 97 264 263 3 363 VSS VDD D0 D1 D2 VSS I/O I/O I/O PWM2M2 PWM1P3 PWM1M3 HVSS HVDD PWM2P3 PWM2M3 I/O I/O I/O I/O I/O HVSS HVDD PWM1P2 PWM1M2 PWM2P2 HVSS I/O I/O I/O PWM2M0 PWM1P1 PWM1M1 HVSS HVDD PWM2P1 PWM2M1 I/O I/O I/O I/O I/O Pin Name PWM1P0 PWM1M0 PWM2P0 HVSS I/O I/O I/O I/O
General Purpose IO Port PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
Circuit Type FV360GA K K K M K K K M not connected K K K M K K K M not connected Q Q Q Q Q Q Ext. Bus Data Bit 0 Ext. Bus Data Bit 1 Ext. Bus Data Bit 2 not connected M K K K M SMC 2 SMC 3 SMC 3 SMC 3 SMC 3 K K K SMC 2 SMC 2 SMC 2 not connected M K K K M SMC 0 SMC 1 SMC 1 SMC 1 SMC 1 F361GA F362GA K K K Function SMC 0 SMC 0 SMC 0
(Continued)
16
MB91360G Series
(Continued) Pin No.
QFP208 186 187 188 189 190 191 192 193 194 195 196 197 200 198 201 202 203 199 204 205 206 207 208 1 2 3 4 5 6 7 8
Pin No. PGA401 314 49 207 151 96 48 262 150 149 362 2 313 47 261 206 360 46 95 1 361 148 205 45 94 260 312 204 147 93 359 311 259 203 146 258 D28 D29 D30 D31 I/O I/O I/O I/O D3 D4 D5 D6 D7 D8 D9 D10 VSS D11 D12 D13 D14 D15 VDD D16 D17 D18 VSS D19 D20 D21 D22 D23 D24 D25 D26 D27 VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name I/O
General Purpose IO Port
Circuit Type FV360GA F361GA F362GA Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Function
not connected Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q not connected Ext. Bus Data Bit 28 Ext. Bus Data Bit 29 Ext. Bus Data Bit 30 Ext. Bus Data Bit 31 17 Ext. Bus Data Bit 3 Ext. Bus Data Bit 4 Ext. Bus Data Bit 5 Ext. Bus Data Bit 6 Ext. Bus Data Bit 7 Ext. Bus Data Bit 8 Ext. Bus Data Bit 9 Ext. Bus Data Bit 10 Ext. Bus Data Bit 11 Ext. Bus Data Bit 12 Ext. Bus Data Bit 13 Ext. Bus Data Bit 14 Ext. Bus Data Bit 15 Ext. Bus Data Bit 16 Ext. Bus Data Bit 17 Ext. Bus Data Bit 18 Ext. Bus Data Bit 19 Ext. Bus Data Bit 20 Ext. Bus Data Bit 21 Ext. Bus Data Bit 22 Ext. Bus Data Bit 23 Ext. Bus Data Bit 24 Ext. Bus Data Bit 25 Ext. Bus Data Bit 26 Ext. Bus Data Bit 27
MB91360G Series
s I/O CIRCUIT TYPE
Type Circuit type Remarks * I/O, CMOS Automotive Schmitt-Trigger Input, STOP control, IOH = 4 mA, IOL = 4 mA
P
Digital output
A
R
N VSS
Digital output
Digital input Stop control
Analog input
R
P
Digital output
* I/O, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control, IOH = 4 mA, IOL = 4 mA
B
R
N VSS
Digital output
Digital input Stop control
* Analog output
VCC P
C
N VSS Analog output
* Analog Input
VCC P
D
R N VSS Analog input
(Continued)
18
MB91360G Series
(Continued) Type
VCC P P
Circuit type
VCC
Remarks * CMOS Schmitt-Trigger Input, Pullup Resistor: 50 k
E
R VSS
N VSS Digital input
* CMOS Schmitt-Trigger Input
VCC P
F
R
N VSS
Digital input
VCC P Digital output
* Tristate Output, IOH = 4 mA, IOL = 4 mA
G
N VSS Digital output
* 4 MHz Oscillator Pin
X1 Clock input
H
X0
Stop control
(Continued)
19
MB91360G Series
(Continued) Type
Circuit type
Remarks * 32 kHz Oscillator Pin
X1A Clock input
I
X0A
Stop control
P
Digital output
* I/O, CMOS Automotive Schmitt-Trigger Input, STOP control (LED) , IOH = 14 mA, IOL = 24 mA
J
R
N VSS
Digital output
Digital input Stop control
P
Digital output
* I/O, CMOS Automotive Schmitt-Trigger Input, STOP control (SMC) , IOH = 30 mA, IOL = 30 mA * Typ. slew rate of 40 ns
K
R
N VSS
Digital output
Digital input Stop control
VCC P Digital output
* I/O, CMOS Input; 5 V or 3 V input, IOH = 4 mA, IOL = 4 mA
L
R
N VSS
Digital output
Digital input
(Continued)
20
MB91360G Series
(Continued) Type
Circuit type
Analog input
Remarks * I/O, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control (SMC) , IOH = 30 mA, IOL = 30 mA * Typ. slew rate of 40 ns
R
P
Digital output
M
R
N VSS
Digital output
Digital input Stop control
Digital input
VCC R
N
N VSS
P
Digital output
* I/O, CMOS Input, Pulldown Resistor: 50 k, 5 V or 3 V input, IOH = 4 mA, IOL = 4 mA
N
Digital output
Digital input
* CMOS Input, Pulldown Resistor: 50 k, 5 V or 3 V input
VCC R
VCC P
O
N VSS
N VSS
* CMOS Input; 3 V input
VCC P
P
R
N VSS
Digital input
(Continued)
21
MB91360G Series
(Continued) Type
Circuit type
Remarks * I/O CMOS Input, STOP control, IOH = 4 mA, IOL = 4 mA
P
Digital output
Q
R
N VSS
Digital output
Digital input Stop control
VCC P P Digital output
* I/O, CMOS Schmitt-Trigger Input, STOP control, Pullup Resistor : 10 k, IOH = 4 mA, IOL = 4 mA
S
R VSS
N
Digital output
Digital input Stop control
* CMOS Input * can withstand high VID for flash programming
T
Control signal MD Input R
VCC P P
VCC
* CMOS Schmitt-Trigger Input, Pullup Resistor: 50 k, 3 V and 5 V input to the core
U
R VSS
N VSS Digital input
(Continued)
22
MB91360G Series
(Continued) Type
VCC P P Digital output
Circuit type
Remarks * I/O, CMOS Schmitt-Trigger Input, STOP control, Pullup Resistor: 50 k,, IOH = 4 mA, IOL = 4 mA
V
R VSS
N
Digital output
Digital input Stop control
3V P Digital output
* I/O, CMOS Input; 3 V input
W
R
N VSS
Digital output
Digital input
* Tristate Output, 3 V
3V P Digital output
X
N VSS Digital output
P
Digital output
* I/O CMOS Input, STOP control, IOH = 3 mA, IOL = 3 mA, in I2C mode operating as open drain outputs
Y
R
N VSS
Digital output
Digital input Stop control
Note : Symbols used in circuit types (Common to all circuit diagrams) P : P channel transistor N : N channel transistor R : Diffusion resistor 23
MB91360G Series
Circuit Type A B C D E F G H I J K L M N O P Q R S T U W X Y
Description I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, STOP control I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control Analog Output Analog Input CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 k, CMOS Schmitt-Trigger Input Tristate Output, IOH = 4 mA / IOL = 4 mA 4 MHz Oscillator Pin 32 kHz Oscillator pin I/O, IOH = 14 mA / IOL = 24 mA, CMOS Automotive Schmitt-Trigger Input, STOP control (LED) I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, STOP control, slew rate improved for EMC (SMC) I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input; 5 V or 3 V input I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control, slew rate improved for EMC (SMC) I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, Pulldown Resistor: 50 k,; 5 V or 3 V input CMOS Input, Pulldown Resistor: 50 k,; 5 V or 3 V input CMOS Input; 3 V input I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control AVRL / AVRH Input I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control, Pull-up Resistor: 10 k, CMOS Input, can withstand VID for flash programming CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 k,, 3.3 V and 5 V inputs to core I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input; 3 V input Tristate Output, IOH = 4 mA / IOL = 4 mA, 3 V I/O, IOH = 3 mA / IOL = 3 mA (I2C) , CMOS Input, STOP control
24
MB91360G Series
s HANDLING DEVICES
1. Preventing latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VDD or less than VSS is applied to an input or output pin or if the voltage applied between VDD and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation.
2. Connecting unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more than 2 KOhm. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at the not used pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up will flow through those diodes.
3. External reset input
When inputting an "L" level to the INIT pin, hold this low level at the INIT pin long enough so that after release of the low level at INIT and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. INIT must be pulled low for at least 8 cycles of the 4 MHz oscillation clock.
4. Power supply pins
All VDD pins should be connected to the same potential (exception can be the external bus interface on F361GA and F362GA) . The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If the external bus interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital voltage has been switched on. If the supply voltage to the external bus interface is switched off (it may not be tristate but should be pulled low) it must be made sure that all related signals do not have a voltage higher than this pulled down supply. When multiple VDD and VSS pins are provided, be sure to connect all VDD and VSS pins to the power supply or ground externally. Although pins at the same potential are connected together in the internal device design so as to prevent malfunctions such as latch-up, connecting all VDD and VSS pins appropriately minimizes unwanted radiation, prevents malfunction of strobe signals due to increases in the ground level, and keeps the overall output current rating. Also, take care to connect VDD and VSS to current source in the lowest possible impedance. Connection of a ceramic bypass capacitor of approximately 0.1 F between VDD and VSS close to the device is recommended. The MB91360G series contains a regulator. To use the device with the 5-V power supply, supply 5-V power to the VCC pins and be sure to connect a bypass capacitor of 10 F parallel to 10 nF to the VCC3C pin for the regulator. [Use with 5-V power supply]
5V 5V VCC AVCC 10 F AVRH AVSS VSS GND 10 nF VCC3C
25
MB91360G Series
5. Crystal oscillator circuit
Noise in the vicinity of the X0 and X1 pins can be a cause of device malfunction. Design the circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. A printed circuit board design that surrounds the X0 and X1 pins with ground provides for stable operation and is strongly recommended.
6. Mode pins
Connect the mode pins (MD0 to MD2) directly to VDD or VSS. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VDD or VSS and to provide a low-impedance connection.
7. Turning the power supply on
Immediately after power on always execute INIT at the INIT pin (start with a low level at the INIT pin) . Hold this low level at the INIT pin long enough so that after release of the low level at INIT and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. INIT must be pulled low for at least 8 cycles of the 4 MHz oscillation clock. The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If the external bus interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital voltage has been switched on.
8. A state in turning power on
Output pin level is not guranteed while supply voltage does not reach minimum operation voltage in turning power on.
26
MB91360G Series
s BLOCK DIAGRAM
Clock Generation FR50 Core Watchdog Timer
User RAM D-bus
32 Instruction Cache/RAM
32 Bit Search Module
F-bus RAM 32 32
Boot ROM 2 KB
DMA Controller
Bus Converter
on FV360GA, F362GA Flashmemory on F361GA 32
R-Bus Adapter
External Bus Interface
CAN
16 SIO Prescaler/ SIO ADC DAC
External Interrupt
U-Timer/ UART
Subclock Calibration
I2C
Reload Timer
Alarm Comparator
Real Time Clock
Power Down Reset
ICU
FreeRunning Timer
OCU
Voltage regulator
LED
Sound Generator
Stepper Motor Control
Prog. Pulse Generator
27
MB91360G Series
s CPU CORE
1. Memory Space
00 : 0000 Direct 00 : 03FF IO Area 00 : 07FF 00 : 1000 00 : 1024 Internal memory area 01 : 1000 01 : 1FFF 03 : C000 D-bus RAM 03 : FFFF 04 : 0000 04 : 3FFF 05 : 0000 05 : 07FF 08 : 0000 128 K 128 K 128 K 64 K 0F : 4000 0F : FFFF 10 : 0000 10 : 07FF 18 : 0000 128 K 128 K 128 K 64 K 16 K 1F : 4000 1F : FFFF 16 K 32 K Bootsector Flash Memory on external bus (F361GA) CAN 16 K 16 K 32 K Bootsector Fixed Reset Vector Flash Memory on F-bus (FV360GA, F362GA) Boot ROM F-bus RAM DMA I-RAM
Direct (short) addressing 0..0FF : Byte access 0..1FF : Halfword access (16 bit) 0..3FF : Word access (32 bit)
01 : 1000 - 01 : 1400 on F361GA
03 : D000 - 03 : FFFF on F361GA, F362GA
04 : 0000 - 04 : 0FFF on F361GA, F362GA 0F : F000 - 0F : F7FF on F361GA
Addresses for CAN and flash memory on external bus depend on settings for the chip select areas CS7 and CS1 respectively. The addresses given here are valid for the CS1 and CS7 settings done in the Boot ROM.
28
MB91360G Series
2. Dedicated Registers
Each of the dedicated registers is used for a particular purpose. The dedicated registers consist of the program counter (PC) , program status (PS) , table base register (TBR) , return pointer (RP) , system stack pointer (SS P) , user stack pointer (USP) , and multiplication and division result registers (MDH/MDL) .
32 bits Program counter PC
Initial value
XXXX XXXXH (Indeterminate)
Program status
PS
Table base register
TBR
000F FC00H XXXX XXXXH (Indeterminate) 0000 0000H XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate)
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication and division results resisters
MDH MDL
(1) Program status (PS)
Bit position
31
20
16
10
87
0
ILM
SCR
CCR
CCR : Condition Code Register SCR : System Condition Code Register ILM : Interrupt Level Mask
29
MB91360G Series
(2) Condition Code Register (CCR) (Bit)
7 6 5 S 4 I 3 N 2 Z 1 V 0 C
Initial value --00XXXXB
(3) System Condition Code Register (SCR) (Bit) 10
D1 9 D0 8 T
Initial value XX0B
(4) Interrupt Level Mask Register (ILM) (Bit)
20 19 18 17 16
Initial value 01111B
ILM4 ILM3 ILM2 ILM1 ILM0
30
MB91360G Series
3. General-Purpose Registers
The general-purpose registers are CPU registers R0 to R15. The register are used as the accumulator for operations and as pointers (a field indicating an address) for memory access. The user can specify the purpose for which the general-purpose registers are used. Register bank structure
32-bits Initial value
R0 R1
XXXX XXXXH
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0000 0000H
Among 16 general-purpose registers, the following registers assume a special purpose. This enhances some instructions. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) The initial value of R0 to R14 after a reset is indeterminate. The initial value of R15 is 00000000H (SSP value) .
31
MB91360G Series
s MODE SETTING
The FR50 series of devices uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode. (1) Mode Pins Three mode pins (MD2 to MD0) are used to specify the reset mode vector access area. Mode Pins Reset vector Mode name Remarks access area MD2 MD1 MD0 0 0 0 0 0 1 Internal ROM mode vector External ROM mode vector Internal External The mode register is used to set the bus width. Reserved
remaining settings (2) Mode Register (MODR)
The data to be written to 0000_7FDH using mode vector fetch is called mode data. MODR is located at 0000_07FDH. After an operation mode has been set in MODR, the device operates in this operation mode. MODR is set only when a reset factor (INIT level) occurs. User programs cannot write data to MODR. < Mode Register (MODR) > Address 0000 07FDH
7 0 6 0 5 0 4 0 3 0 2 ROMA 1 WTH1 0 WTH0
Initial value XXXXXXXX
Operation mode setting bit
[Bits 7 to 3] : (Reserved bits) Always set 00000 at bits 7 to 3. Operation is not guaranteed when other values are set. [Bit 2] : ROMA (internal ROM enable bit) The ROMA bit is used to set whether to validate the internal ROM area (Fbus memory area) . ROMA Function Remarks 0 1 External ROM mode Internal ROM mode Access to the Fbus area is external.
32
MB91360G Series
[Bits 1 and 0] : WTH1 and WTH0 (bus width/single chip mode specifying bits) The WTH1 and WTH0 bits are used to set the bus width (valid when operation mode is external bus mode) and the single chip mode. When the operation mode is the external bus mode, this value is set at the BW1 and BW0 bits of AMD0 (CS0 area) . WTH1 WTH0 Function Remarks 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width 32-bit bus width Single chip mode External bus mode External bus mode External bus mode
(3) Fixed Vector If MB91360 series devices are started in mode MD[2 : 0] = 000, the internal fixed mode vector (FMV = 0x06) and the fixed reset vector are used. The fixed reset vector points to the start address of the internal Boot ROM. This enables access to the F-bus area, to the internal CAN modules and the internal flash memory. See also section Boot ROM.
33
MB91360G Series
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H SSR0 [R/W] 00001 - 00 ULS0 [R/W] - - - - 0000 EIRR [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R/W] 0 - - 11111 PDRG [R/W] XXXXXXXX PDRK [R/W] XXXXXXXX PDRO [R/W] XXXXXXXX PDRS [R/W] XXXXXXXX PDRH [R/W] XXXXXXXX PDRL [R/W] XXXXXXXX PDRP [R/W] - - XXXXX ELVR [R/W] 00000000 00000000 CLKR2 [R/W] - - - - - 000 reserved Register +0 reserved reserved PDR8 [R/W] - - - - - XX +1 reserved reserved PDR9 [R/W] XXXXXXX1 PDRI [R/W] X---X--PDRM [R/W] - - - - XXXX PDRQ [R/W] - - XXXXX PDRJ [R/W] XXXXXXXX PDRN [R/W] - - XXXXXX PDRR [R/W] XXXXXXXX Reserved R-bus Port Data Register +2 reserved reserved +3 reserved PDR7 [R/W] -111 - - - PDRB [R/W] - - - - - XXX T-unit Port Data Register Block
Ext int/NMI DLYI/I-unit RTC
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX TMRLR2 [W] XXXXXXXX XXXXXXXX SIDR0 [R/W] XXXXXXXX
TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] - - - - 0000 - - - 00000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] - - - - 0000 - - - 00000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] - - - - 0000 - - - 00000 SCR0 [R/W] 00000100 SMR0 [R/W] 00 - - 0 - 0
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0
(Continued)
34
MB91360G Series
(Continued)
Address 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H IBCR [R/W] 00000000 ADMD [R/W, W] - - - X0000 IBSR [R] 00000000 IDAR [R/W] XXXXXXXX ADCH [R/W] 00000000 Register +0 +1 +2 DRCL0 [W] -------SCR1 [R/W] 00000100 DRCL1 [W] -------SCR2 [R/W] 00000100 DRCL2 [W] -------SES0 [R/W] - - - - - - 00 SES1 [R/W] - - - - - - 00 CDCR1 [R/W] 0 - - - 1111 IADR [R/W] -XXXXXXX ICCR [R/W] - - 0XXXXX IDBL [R/W] -------0 ADCS [R/W, W] 0000 - - 00 ADBL [R/W] -------0 +3 UTIMC0 [R/W] 0 - - - 0 - 01 SMR1 [R/W] 00 - - 0 - 0 UTIMC1 [R/W] 0 - - - - - 01 SMR2 [R/W] 00 - - 0 - 0 UTIMC2 [R/W] 0 - - - 0 - 01 SDR0 [R/W] 00000000 SDR1 [R/W] 00000000 Reserved U-TIMER2 SIO 0 SIO 1 SIO 0/1 Prescaler Reserved I2C (old) new I2C from addr 0x184 U-TIMER 1 UTIM0/UTIMR0 [R/W] 00000000 00000000 SSR1 [R/W] 00001 - 00 ULS1 [R/W] - - - - 0000 SIDR1 [R/W] XXXXXXXX Block U-TIMER 0
UART1
UTIM1/UTIMR1 [R/W] 00000000 00000000 SSR2 [R/W] 00001 - 00 ULS2 [R/W] - - - - 0000 SIDR2 [R/W] XXXXXXXX
UART2
UTIM2/UTIMR2 [R/W] 00000000 00000000 SMCS0 [R/W] 00000010 - - - - 00-0 SMCS1 [R/W] 00000010 - - - - 00 - 0 CDCR0 [R/W] 0 - - - 1111 Reserved
ADCD [R/W] 000000XX XXXXXXXX DACR [R/W] - - - - - 000
A/D Converter
DADR0 [R/W] - - - - - - XX XXXXXXXX IOTDBL1 [R/W] - - - - - 000 DDBL [R/W] -------0 ICS23 [R/W] 00000000
DADR1 [R/W] - - - - - - XX XXXXXXXX IOTDBL0 [R/W] - - - - - 000 ICS01 [R/W] 00000000
DAC
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX
Input Capture 0, 1, 2, 3
(Continued)
35
MB91360G Series
(Continued)
Address 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H TCDT0 [R/W] XXXXXXXX XXXXXXXX TCDT1 [R/W] XXXXXXXX XXXXXXXX ZPD0 [R/W] 00000010 ZPD2 [R/W] 00000010 PWC20 [R/W] XXXXXXXX PWC21 [R/W] XXXXXXXX PWC22 [R/W] XXXXXXXX PWC23 [R/W] XXXXXXXX SMDBL0 [R/W] -------0 SGAR [R/W] 00000000 WTHR [R/W] - - - 00000 PWC0 [R/W] - - 000 - - 0 PWC2 [R/W] - - 000 - - 0 PWC10 [R/W] XXXXXXXX PWC11 [R/W] XXXXXXXX PWC12 [R/W] XXXXXXXX PWC13 [R/W] XXXXXXXX SMDBL1 [R/W] ------0 SGDBL [R/W] -------0 SGFR [R/W] XXXXXXXX WTDBL [R/W] -------0 Register +0 +1 +2 reserved OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX TCCS0 [R/W] - 0000000 TCCS1 [R/W] - 0000000 PWC1 [R/W] 00000 - - 0 PWC3 [R/W] 00000 - - 0 PWS10 [R/W] - - 000000 PWS11 [R/W] - - 000000 PWS12 [R/W] - - 000000 PWS13 [R/W] - - 000000 SMDBL3 [R/W] -------0 Reserved Free Running Counter 0 for ICU/OCU Free Running Counter 1 for ICU/OCU SMC 0, 1 SMC 2, 3 SMC 0 SMC 1 SMC 2 SMC 3 SMC 0, 1, 2, 3 Output Compare 0, 1, 2.3 +3 OCS0/1 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX Block
0000CCH
ZPD1 [R/W] 00000010 ZPD3 [R/W] 00000010 PWS20 [R/W] - 0000000 PWS21 [R/W] - 0000000 PWS22 [R/W] - 0000000 PWS23 [R/W] - 0000000 SMDBL2 [R/W] -------0
0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H
SGCR [R, R/W] 0 - - - - - 00 000 - - 000 SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX
Sound generator
WTCR [R, R/W] 00000000 000 - 0000 Real Time Clock (WatchTimer)
WTBR [R/W] - - XXXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 WTSR [R/W] - - 000000
TMRLR3 [W] XXXXXXXX XXXXXXXX
TMR3 [R] XXXXXXXX XXXXXXXX TMCSR3 [R/W] - - - - XX - - - - - XXXXX
Reload Timer 3
(Continued)
36
MB91360G Series
(Continued)
Address 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 000144H 000148H 00014CH 000150H 000154H Register +0 +1 +2 +3 TMRLR4 [W] XXXXXXXX XXXXXXXX TMRLR5 [W] XXXXXXXX XXXXXXXX GCN10 [R/W] 00110010 00010000 GCN11 [R/W] 00110010 00010000 PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX PTMR4 [R] 11111111 11111111 PDUT4 [W] XXXXXXXX XXXXXXXX PTMR5 [R] 11111111 11111111 PDUT5 [W] XXXXXXXX XXXXXXXX PTMR6 [R] 11111111 11111111 PDUT 6 [W] XXXXXXXX XXXXXXXX TMR4 [R] XXXXXXXX XXXXXXXX TMCSR4 [R/W] - - - - XX - - - - - XXXXX TMR5 [R] XXXXXXXX XXXXXXXX TMCSR5 [R/W] - - - - XX - - - - - XXXXX PDBL0 [R/W] - - - 00000 PDBL1 [R/W] - - - 00000 GCN20 [R/W] - - - - 0000 GCN21 [R/W] - - - - 0000 Block
Reload Timer 4
Reload Timer 5
PWM Control 0 PWM Control 1
PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 0000000 PCNL0 [R/W] 000000 - 0
PWM0
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 0000000 PCNL1 [R/W] 000000 - 0
PWM1
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 0000000 PCNL2 [R/W] 000000 - 0
PWM2
PCSR3 [W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 0000000 PCNL3 [R/W] 000000 - 0
PWM3
PCSR4 [W] XXXXXXXX XXXXXXXX PCNH4 [R/W] 0000000 PCNL4 [R/W] 000000 - 0
PWM4
PCSR5 [W] XXXXXXXX XXXXXXXX PCNH5 [R/W] 0000000 PCNL5 [R/W] 000000 - 0
PWM5
PCSR6 [W] XXXXXXXX XXXXXXXX PCNH6 [R/W] 0000000 PCNL6 [R/W] 000000 - 0
PWM6
(Continued)
37
MB91360G Series
(Continued)
Address 000158H 00015CH 000160H 000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H 000198H to 0001F8H 0001FCH 000200H 000204H CMCR [R/W] 11111111 0000000 CMLS0 [R/W] 01110111 1111111 CMLS2 [R/W] 01110111 1111111 CMLT0 [R/W] - - - - -100 00000010 CMLT2 [R/W] - - - - -100 00000010 CMAC [R/W] 11111111 1111111 ACCDBL[R/W] -------0 IBCR2 [R/W, W] 00000000 ITMKH [R/W, W] 00 - - - - 11 IDARH [-] 00000000 PDRCR [R/W] - - - - - 000 ACSR [R, R/W] - - - XXX00 IBSR2 [R] 00000000 ITMKL [R/W] 11111111 IDAR2 [R/W] 00000000 Register +0 +1 +2 +3 PTMR7 [R] 11111111 11111111 PDUT7 [W] XXXXXXXX XXXXXXXX CMPR [R/W] - - - -1001 1 - - -0001 CMLS1 [R/W] 01110111 1111111 CMLS3 [R/W] 01110111 1111111 CMLT1 [R/W] 11110100 00000010 CMLT3 [R/W] - - - - -100 00000010 CMTS [R/W] - -000001 01111111 ITBAH [R/W] - - - - - - 00 ISMK [R/W] 01111111 ICCR2 [R/W] - 0011111 ITBAL [R/W] 00000000 ISBA [R/W] - 0000000 IDBL2 (*) [R/W] -------0 Calibration Unit of 32 kHz oscillator I2C (new) Power down reset Alarm comparator PCSR7 [W] XXXXXXXX XXXXXXXX PCNH7 [R/W] 0000000 PCNL7 [R/W] 000000 - 0 Block
PWM7
Reserved
Clock Modulation
CUCR [R, R/W] - - - - - - - - - - - 0 - -00 CUTR1 [R] - - - - - - - - 00000000
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000
Reserved F362MD [R/W] 00000000 F362GA Mode Register
DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX
DMAC
* : Old and new I2C share this bit.
(Continued)
38
MB91360G Series
(Continued)
Address 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 0002FCH 000300H 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003ECH Register +0 +1 +2 +3 DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACR [R/W] 00 - - 0000 - - - - - - - - - - - - - - - - - - - - - - - IRBS 00000000 00000001 00100000 - - - - - - - ICHRC 0-000000 ISIZE [R/W] - - - - - -11 Reserved DMAC Block
Instruction Cache
Reserved
Instruction Cache
Reserved
(Continued)
39
MB91360G Series
(Continued)
Address 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H ICR00 [R, R/W] - - -11111 ICR04 [R, R/W] - - -11111 ICR08 [R, R/W] - - -11111 ICR12 [R, R/W] - - -11111 ICR16 [R, R/W] - - -11111 ICR20 [R, R/W] - - -11111 ICR24 [R, R/W] - - -11111 ICR01 [R, R/W] - - -11111 ICR05 [R, R/W] - - -11111 ICR09 [R, R/W] - - -11111 ICR13 [R, R/W] - - -11111 ICR17 [R, R/W] - - -11111 ICR21 [R, R/W] - - -11111 ICR25 [R, R/W] - - -11111 Register +0 +1 +2 +3 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG [R/W] 00000000 DDRK [R/W] 00000000 DDRO [R/W] 00000000 DDRS [R/W] 00000000 PFRG [R/W] 00000000 PFRK [R/W] 00000000 PFRO [R/W] 00000000 PFRS [R/W] 00000000 DDRH [R/W] 00000000 DDRL [R/W] 00000000 DDRP [R/W] - - - -0000 PFRH [R/W] 00000000 PFRL [R/W] 00000000 PFRP [R/W] 00000000 ICR02 [R, R/W] - - -11111 ICR06 [R, R/W] - - -11111 ICR10 [R, R/W] - - -11111 ICR14 [R, R/W] - - -11111 ICR18 [R, R/W] - - -11111 ICR22 [R, R/W] - - -11111 ICR26 [R, R/W] - - -11111 ICR03 [R, R/W] - - -11111 ICR07 [R, R/W] - - -11111 ICR11 [R, R/W] - - -11111 ICR15 [R, R/W] - - -11111 ICR19 [R, R/W] - - -11111 ICR23 [R, R/W] - - -11111 ICR27 [R, R/W] - - -11111 Interrupt Control unit DDRI [R/W] - - - -0- - DDRM [R/W] - - - -0000 DDRQ [R/W] - -000000 PFRI [R/W] - - - -0- - PFRM [R/W] - - - -0000 PFRQ [R/W] - -000000 DDRJ [R/W] 00000000 DDRN [R/W] - -000000 DDRR [R/W] 00000000 PFRJ [R/W] 00000000 PFRN [R/W] - -000000 PFRR [R/W] 00000000 Reserved R-bus Port Function Register R-bus Port Direction Register Bit Search Module Block
(Continued)
40
MB91360G Series
(Continued)
Address 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H to 00063FH PFR8 [R/W] 111110-0 PFR9 [R/W] 11110101 PFR27 [R/W] 1111-00Reserved DDR8 [R/W] 00000000 DDR9 [R/W] 00000000 PFR7 [R/W] 00001111 PFRB [R/W] 00000000 T-unit Port Function Register RSRR [R/W] 10000000 CLKR [R/W] 00000000 STCR [R/W] 00110011 WPR [W] XXXXXXXX DDR7 [R/W] 00000000 DDRB [R/W] 00000000 T-unit Port Direction Register Register +0 ICR28 [R, R/W] - - -11111 ICR32 [R, R/W] - - -11111 ICR36 [R, R/W] - - -11111 ICR40 [R, R/W] - - -11111 ICR44 [R, R/W] - - -11111 +1 ICR29 [R, R/W] - - -11111 ICR33 [R, R/W] - - -11111 ICR37 [R, R/W] - - -11111 ICR41 [R, R/W] - - -11111 ICR45 [R, R/W] - - -11111 TBCR [R/W] X0000X00 DIVR0 [R/W] 00000011 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 +2 ICR30 [R, R/W] - - -11111 ICR34 [R, R/W] - - -11111 ICR38 [R, R/W] - - -11111 ICR42 [R, R/W] - - -11111 ICR46 [R, R/W] - - -11111 +3 ICR31 [R, R/W] - - -11111 ICR35 [R, R/W] - - -11111 ICR39 [R, R/W] - - -11111 ICR43 [R, R/W] - - -11111 ICR47 [R, R/W] - - -11111 Reserved Interrupt Control unit Block
Clock Control unit
Reserved
(Continued)
41
MB91360G Series
(Continued)
Address 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H ESTS0 X0000000 ECTL0 0X000000 ECNT0 XXXXXXXX ESTS1 XXXXXXXX ECTL1 00000000 ECNT1 XXXXXXXX MODR [W] XXXXXXXX ESTS2 XXXXXXXX ECTL2 000X0000 EUSA XXX0000X ECTL3 00000X11 EDTC 0000XXXX DSU CHE [R/W] 11111111 Register +0 +1 +2 +3 ASR0 [W] 00000000 00000000 ASR1 [W] 00000000 00000000 ASR2 [W] 00000000 00000000 ASR3 [W] 00000000 00000000 ASR4 [W] 00000000 00000000 ASR5 [W] 00000000 00000000 ASR6 [W] 00000000 00000000 ASR7 [W] 00000000 00000000 AMD0 [R/W] -00XX111 AMD4 [R/W] - -XXXXXX CSE [R/W] 11000011 AMD1 [R/W] -XXXXXXX AMD5 [R/W] - -XXXXXX AMR0 [W] 11111000 11111111 AMR1 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 AMR4 [W] 00000000 00000000 AMR5 [W] 00000000 00000000 AMR6 [W] 00000000 00000000 AMR7 [W] 00000000 00000000 AMD2 [R/W] - -XXXXXX AMD6 [R/W] -XXXXXXX Reserved AMD3 [R/W] - -XXXXXX AMD7 [R/W] -XXXXXXX T-unit Block
Mode Register
Reserved
(Continued)
42
MB91360G Series
(Continued)
Address 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H Register +0 +1 +2 EDTR1 XXXXXXXX XXXXXXXX EIA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSU +3 EWPT XXXXXXXX XXXXXXXX EDTR0 XXXXXXXX XXXXXXXX Block
(Continued)
43
MB91360G Series
(Continued)
Address 000B64H 000B68H 000B6CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 003FFCH 004000H to 006FFFH 007000H 007004H 007008H to 00FFFCH FMCS [R/W] 1110X000 FMWT [R/W] - -000011 Register +0 +1 +2 +3 EOAM1/EODM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved DSU Block
DMAC

Reserved Flash Memory Control Register on F362GA/ FV360GA Reserved
(Continued)
44
MB91360G Series
(Continued)
Address 010000H to 010FFCH 011000H to 011FFCH 012000H to 01FFFCH 020000H to 03BFFCH 03C000H to 03FFFCH 040000H to 043FFCH 044000H to 0FEFFC 050000H to 0507FCH 050800H to 07FFF4H 080000H to 09FFFCH 0A0000H to 0BFFFC 0C0000H to 0DFFFC 0E0000H to 0EFFFC 0F0000H to 0F3FFCH Sector 0 64 KB Sector 1 64 KB Sector 2 64 KB Sector 3 32 KB Sector 4 8 KB Register +0 +1 +2 +3 (for exact address range see "s PERIPHERAL RESOURCES 1. INSTRUCTION CACHE") on F361GA only 1 K Cache is available, on F362GA no cache, but 4 K I-RAM are available Block
I-Cache 4 KB
Reserved
Reserved
Reserved User RAM 16 KB (D-Bus) Fast RAM 16 KB (F-Bus) Reserved Boot ROM 2 KB (F-Bus) reserved
Only first 12 KB are available on F362GA and F361GA
Only first 4 K are available on F362GA and F361GA
Sector 7 64 KB Sector 8 64 KB Sector 9 64 KB Sector 10 32 KB Sector 11 8 KB
Flash Memory 512 K on F-Bus on FV360GA and F362GA
(Continued)
45
MB91360G Series
(Continued)
Address 0F4000H to 0F7FFCH 0F8000H to 0FFFF4H 0FFFF8H 0FFFFCH Register +0 Sector 5 8 KB Sector 6 16 KB FMV [R] 06 00 00 00H FRV [R] 00 05 00 00H on FV360GA/F362GA / 00 FF 00 00 on F361GA +1 +2 Sector 12 8 KB Sector 13 16 KB +3 Block Flash Memory 512 K on F-Bus on FV360GA and F362GA Fixed Reset/Mode Vector
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
(Continued)
46
MB91360G Series
(Continued)
Address 100000H 100004H 100008H 10000CH 100010H 100014H 100018H 10001CH 100020H 100024H 100028H 10002CH to 10004BH 10004CH 100050H 100054H 100058H 10005CH 100060H 100064H 100068H Register +0 +1 +2 +3 BVALR0 [R/W] 00000000 00000000 TCANR0 [W] 00000000 00000000 RCR0 [R/W] 00000000 00000000 ROVRR0 [R/W] 00000000 00000000 CSR0 [R/W, R] 00000000 00000001 RTEC0 [R] 00000000 00000000 IDER0 [R/W] XXXXXXXX XXXXXXXX RFWTR0 [R/W] XXXXXXXX XXXXXXXX TREQR0 [R/W] 00000000 00000000 TCR0 [R/W] 00000000 00000000 RRTRR0 [R/W] 00000000 00000000 RIER0 [R/W] 00000000 00000000 LEIR0 [R/W] 000-0000 Block
BTR0 [R/W] -1111111 11111111 TRTRR0 [R/W] 00000000 00000000 TIER0 [R/W] 00000000 00000000 CAN 0 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents.
AMSR0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR00 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX AMR10 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX GENERAL PURPOSE RAM [R/W] IDR00 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR10 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR20 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR30 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR40 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR50 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR60 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR70 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
(Continued)
47
MB91360G Series
(Continued)
Address 10006CH 100070H 100074H 100078H 10007CH 100080H 100084H 100088H 10008CH 100090H 100094H 100098H 10009CH 1000A0H 1000A4H 1000A8H Register +0 +1 +2 +3 IDR80 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR90 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR100 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR110 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR120 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR130 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR140 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR150 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX DLCR00 [R/W] - - - - - - - - - - - - XXXX DLCR20 [R/W] - - - - - - - - - - - - XXXX DLCR40 [R/W] - - - - - - - - - - - - XXXX DLCR60 [R/W] - - - - - - - - - - - - XXXX DLCR80 [R/W] - - - - - - - - - - - - XXXX DLCR100 [R/W] - - - - - - - - - - - - XXXX DLCR120 [R/W] - - - - - - - - - - - - XXXX DLCR140 [R/W] - - - - - - - - - - - - XXXX DLCR10 [R/W] - - - - - - - - - - - - XXXX DLCR30 [R/W] - - - - - - - - - - - - XXXX DLCR50 [R/W] - - - - - - - - - - - - XXXX DLCR70 [R/W] - - - - - - - - - - - - XXXX DLCR90 [R/W] - - - - - - - - - - - - XXXX DLCR110 [R/W] - - - - - - - - - - - - XXXX DLCR130 [R/W] - - - - - - - - - - - - XXXX DLCR150 [R/W] - - - - - - - - - - - - XXXX CAN 0 Block
1000ACH
DTR00 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR20 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000B4H
1000BCH
(Continued)
48
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR30 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR40 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR50 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR60 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR70 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR80 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR90 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR100 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR110 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR120 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR130 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR140 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR150 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG0 [R/W] 00000000 00000110 Block
1000C4H
1000CCH
1000D4H
1000DCH
1000E4H
1000ECH
1000F4H
CAN 0
1000FCH
100104H
10010CH
100114H
10011CH
100124H
10012CH
(Continued)
49
MB91360G Series
(Continued)
Address Register +0 FMCS [R/W] 1 - - 0X000 BVALR1 [R/W] 00000000 00000000 TCANR1 [W] 00000000 00000000 RCR1 [R/W] 00000000 00000000 ROVRR1 [R/W] 00000000 00000000 CSR1 [R/W] 00000000 00000001 RTEC1 [R] 00000000 00000000 IDER1 [R/W] XXXXXXXX XXXXXXXX RFWTR1 [R/W] XXXXXXXX XXXXXXXX +1 +2 -----------------------TREQR1 [R/W] 00000000 00000000 TCR1 [R/W] 00000000 00000000 RRTRR1 [R/W] 00000000 00000000 RIER1 [R/W] 00000000 00000000 LEIR1 [R/W] 000-0000 +3 Block Flash Memory control for F361GA
100180H
100200H 100204H 100208H 10020CH 100210H 100214H 100218H 10021CH 100220H 100224H 100228H 10022CH to 100248H 10024CH 100250H 100254H 100258H 10025CH 100260H
BTR1 [R/W] -1111111 11111111 TRTRR1 [R/W] 00000000 00000000 TIER1 [R/W] 00000000 00000000 CAN 1 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents.
AMSR1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR01 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX AMR11 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX GENERAL PURPOSE RAM [R/W] IDR01 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR11 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR21[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR31 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXXIDR41 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR51 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
(Continued)
50
MB91360G Series
(Continued)
Address 100264H 100268H 10026CH 100270H 100274H 100278H 10027CH 100280H 100284H 100288H 10028CH 100290H 100294H 100298H 10029CH 1002A0H 1002A4H 1002A8H Register +0 +1 +2 +3 IDR61 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR71 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR81 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR91 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR101 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR111 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - IDR131 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR141 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR151 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX DLCR01 [R/W] - - - - - - - - - - - - XXXX DLCR21 [R/W] - - - - - - - - - - - - XXXX DLCR41 [R/W] - - - - - - - - - - - - XXXX DLCR61 [R/W] - - - - - - - - - - - - XXXX DLCR81[R/W] - - - - - - - - - - - - XXXX DLCR101 [R/W] - - - - - - - - - - - - XXXX DLCR121 [R/W] - - - - - - - - - - - - XXXX DLCR141 [R/W] - - - - - - - - - - - - XXXX DLCR11 [R/W] - - - - - - - - - - - - XXXX DLCR31 [R/W] - - - - - - - - - - - - XXXX DLCR51 [R/W] - - - - - - - - - - - - XXXX DLCR71 [R/W] - - - - - - - - - - - - XXXX DLCR91 [R/W] - - - - - - - - - - - - XXXX DLCR111 [R/W] - - - - - - - - - - - - XXXX DLCR131 [R/W] - - - - - - - - - - - - XXXX DLCR151 [R/W] - - - - - - - - - - - - XXXX CAN 1 Block
1002ACH
DTR01 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
51
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR21 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR31 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR41 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR51 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR61 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR71 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR81 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR91 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR101 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR111 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR131 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR141 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block
1002B4H
1002BCH
1002C4H
1002CCH
1002D4H
1002DCH
1002E4H
CAN 1
1002ECH
1002F4H
1002FCH
100304H
10030CH
100314H
10031CH
(Continued)
52
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR151 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG1 [R/W] 00000000 00000110 BVALR2 [R/W] 00000000 00000000 TCANR2 [W] 00000000 00000000 RCR2 [R/W] 00000000 00000000 ROVRR2 [R/W] 00000000 00000000 CSR2 [R/W] 00000000 00000001 RTEC2 [R] 00000000 00000000 IDER2 [R/W] XXXXXXXX XXXXXXXX RFWTR2 [R/W] XXXXXXXX XXXXXXXX TREQR2 [R/W] 00000000 00000000 TCR2 [R/W] 00000000 00000000 RRTRR1 [R/W] 00000000 00000000 RIER2 [R/W] 00000000 00000000 LEIR2 [R/W] 000-0000 Block
100324H
CAN 1
10032CH 100400H 100404H 100408H 10040CH 100410H 100414H 100418H 10041CH 100420H 100424H 100428H 10042CH to 100448H 10044CH 100450H 100454H 100458H 10045CH
BTR2 [R/W] -1111111 11111111 TRTRR2 [R/W] 00000000 00000000 TIER2 [R/W] 00000000 00000000 CAN 2 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents.
AMSR2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR02 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX AMR12 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX GENERAL PURPOSE RAM [R/W] IDR02 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR12 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR22[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR32 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXXIDR42 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
(Continued)
53
MB91360G Series
(Continued)
Address 100460H 100464H 100468H 10046CH 100470H 100474H 100478H 10047CH 100480H 100484H 100488H 10048CH 100490H 100494H 100498H 10049CH 1004A0H 1004A4H 1004A8H Register +0 +1 +2 +3 IDR52 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR62 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR72 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR82 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR92 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR102 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR112 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR122 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - IDR132 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR142 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR152 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX DLCR02 [R/W] - - - - - - - - - - - - XXXX DLCR22 [R/W] - - - - - - - - - - - - XXXX DLCR42 [R/W] - - - - - - - - - - - - XXXX DLCR62 [R/W] - - - - - - - - - - - - XXXX DLCR82[R/W] - - - - - - - - - - - - XXXX DLCR102 [R/W] - - - - - - - - - - - - XXXX DLCR122 [R/W] - - - - - - - - - - - - XXXX DLCR142 [R/W] - - - - - - - - - - - - XXXX DLCR12 [R/W] - - - - - - - - - - - - XXXX DLCR32 [R/W] - - - - - - - - - - - - XXXX DLCR52 [R/W] - - - - - - - - - - - - XXXX DLCR72 [R/W] - - - - - - - - - - - - XXXX DLCR92 [R/W] - - - - - - - - - - - - XXXX DLCR112 [R/W] - - - - - - - - - - - - XXXX DLCR132 [R/W] - - - - - - - - - - - - XXXX DLCR152 [R/W] - - - - - - - - - - - - XXXX CAN 2 Block
1004ACH
DTR02 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
54
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR02 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR22 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR32 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR42 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR52 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR62 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR72 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR82 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR92 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR102 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR112 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR122 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR132 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block
1004ACH
1004B4H
1004BCH
1004C4H
1004CCH
1004D4H
1004DCH
CAN 2
1004E4H
1004ECH
1004F4H
1004FCH
100504H
10050CH
100514H
(Continued)
55
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR142 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR152 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG2 [R/W] 00000000 00000110 BVALR3 [R/W] 00000000 00000000 TCANR3 [W] 00000000 00000000 RCR3 [R/W] 00000000 00000000 ROVRR3 [R/W] 00000000 00000000 CSR3 [R/W] 00000000 00000001 RTEC3 [R] 00000000 00000000 IDER3 [R/W] XXXXXXXX XXXXXXXX RFWTR3 [R/W] XXXXXXXX XXXXXXXX TREQR3 [R/W] 00000000 00000000 TCR3 [R/W] 00000000 00000000 RRTRR31 [R/W] 00000000 00000000 RIER3 [R/W] 00000000 00000000 LEIR3 [R/W] 000-0000 CAN 3 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. CAN 2 Block
10051CH
100524H
10052CH 100600H 100604H 100608H 10060CH 100610H 100614H 100618H 10061CH 100620H 100624H 100628H 10062CH to 100648H 10064CH 100650H 100654H 100658H
BTR3 [R/W] -1111111 11111111 TRTRR3 [R/W] 00000000 00000000 TIER3 [R/W] 00000000 00000000
AMSR3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR03 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX AMR13 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX GENERAL PURPOSE RAM [R/W] IDR03 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR13 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR23[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR33 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX-
(Continued)
56
MB91360G Series
(Continued)
Address 10065CH 100660H 100664H 100668H 10066CH 100670H 100674H 100678H 10067CH 100680H 100684H 100688H 10068CH 100690H 100694H 100698H 10069CH 1006A0H 1006A4H 1006A8H Register +0 +1 +2 +3 IDR43 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR53 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR63 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR73 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR83 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR93 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR103 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR113 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR123 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - IDR133 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR143 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX IDR153 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX DLCR032 [R/W] - - - - - - - - - - - - XXXX DLCR232 [R/W] - - - - - - - - - - - - XXXX DLCR43 [R/W] - - - - - - - - - - - - XXXX DLCR63 [R/W] - - - - - - - - - - - - XXXX DLCR83[R/W] - - - - - - - - - - - - XXXX DLCR103 [R/W] - - - - - - - - - - - - XXXX DLCR123 [R/W] - - - - - - - - - - - - XXXX DLCR143 [R/W] - - - - - - - - - - - - XXXX DLCR13 [R/W] - - - - - - - - - - - - XXXX DLCR33 [R/W] - - - - - - - - - - - - XXXX DLCR53 [R/W] - - - - - - - - - - - - XXXX DLCR733 [R/W] - - - - - - - - - - - - XXXX DLCR93 [R/W] - - - - - - - - - - - - XXXX DLCR113 [R/W] - - - - - - - - - - - - XXXX DLCR133 [R/W] - - - - - - - - - - - - XXXX DLCR153 [R/W] - - - - - - - - - - - - XXXX Block
CAN 3
(Continued)
57
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR03 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR23 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR33 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR43 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR53 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR63 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR73 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR83 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR93 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR103 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR113 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR123 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR133 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block
1006ACH
1006B4H
1006BCH
1006C4H
1006CCH
1006D4H
1006DCH
CAN 3
1006E4H
1006ECH
1006F4H
1006FCH
100704H
10070CH
100714H
(Continued)
58
MB91360G Series
(Continued)
Address Register +0 +1 +2 +3 DTR143 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR153 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG3 [R/W] 00000000 00000110 Sector 0 64 KB Sector 1 64 KB Sector 2 64 KB Sector 3 32 KB Sector 4 8 KB Sector 5 8 KB Sector 6 16 KB Sector 7 64 KB Sector 8 64 KB Sector 9 64 KB Sector 10 32 KB Sector 11 8 KB Sector 12 8 KB Sector 13 16 KB CAN 3 Block
10071CH
100724H
10072CH 180000H to 19FFFCH 1A0000H to 1BFFFC 1C0000H to 1DFFFC 1E0000H to 1 EFFFCH 1F0000H to 1F3FFCH 1F4000H to 1F7FFCH 1F8000H to 1FFFFCH
Flash Memory 512 K on F361GA - addresses depending on settings for ship select area CS1
Note: The data in reserved areas and areas marked "" is indeterminate. Do not use those areas!
59
MB91360G Series
s INTERRUPT CAUSES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTER
Interrupt number Interrupt Reset Mode vector System reserved System reserved System reserved System reserved System reserved Co-processor fault trap INTE instruction *4 Instruction break exception *4 Operand break trap *4 Step trace trap *4 NMI interrupt (tool) *4 Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 Reload Timer 0 Reload Timer 1 Reload Timer 2 CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS
*4
Interrupt level *1 Setting Register FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 0x440 0x441 0x442 0x443 0x444 0x445 0x446 0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E Register address
Interrupt vector *2 Offset 0x3FC 0x3F8 0x3F4 0x3F0 0x3EC 0x3E8 0x3E4 0x3E0 0x3DC 0x3D8 0x3D4 0x3D0 0x3CC 0x3C8 0x3C4 0x3C0 0x3BC 0x3B8 0x3B4 0x3B0 0x3AC 0x3A8 0x3A4 0x3A0 0x39C 0x398 0x394 0x390 0x38C 0x388 0x384 Default Vector address 0x000FFFFC 0x000FFFF8 0x000FFFF4 0x000FFFF0 0x000FFFEC 0x000FFFE8 0x000FFFE4 0x000FFFE0 0x000FFFDC 0x000FFFD8 0x000FFFD4 0x000FFFD0 0x000FFFCC 0x000FFFC8 0x000FFFC4 0x000FFFC0 0x000FFFBC 0x000FFFB8 0x000FFFB4 0x000FFFB0 0x000FFFAC 0x000FFFA8 0x000FFFA4 0x000FFFA0 0x000FFF9C 0x000FFF98 0x000FFF94 0x000FFF90 0x000FFF8C 0x000FFF88 0x000FFF84 RN 4 5 8 9 6 7
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
Co-processor error trap *4
(Continued)
60
MB91360G Series
(Continued)
Interrupt number Interrupt CAN 2 RX CAN 2 TX/NS CAN 3 RX *5 CAN 3 TX/NS PPG 0/1 PPG 2/3 PPG 4/5 PPG 6/7 Reload Timer 3 Reload Timer 4 Reload Timer 5 ICU 0/1 OCU 0/1 ICU 2/3 OCU 2/3 ADC Timebase Overflow Free Running Counter 0 Free Running Counter 1 SIO 0 SIO 1
*6 *6 *5
Interrupt level *1 Setting Register ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 Register address 0x44F 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x45E 0x45F 0x460 0x461 0x462 0x463 0x464 0x465 0x466 0x467 0x468 0x469 0x46A 0x46B 0x46C 0x46D 0x46E
Interrupt vector *2 Offset 0x380 0x37C 0x378 0x374 0x370 0x36C 0x368 0x364 0x360 0x35C 0x358 0x354 0x350 0x34C 0x348 0x344 0x340 0x33C 0x338 0x334 0x330 0x32C 0x328 0x324 0x320 0x31C 0x318 0x314 0x310 0x30C 0x308 0x304 Default Vector address 0x000FFF80 0x000FFF7C 0x000FFF78 0x000FFF74 0x000FFF70 0x000FFF6C 0x000FFF68 0x000FFF64 0x000FFF60 0x000FFF5C 0x000FFF58 0x000FFF54 0x000FFF50 0x000FFF4C 0x000FFF48 0x000FFF44 0x000FFF40 0x000FFF3C 0x000FFF38 0x000FFF34 0x000FFF30 0x000FFF2C 0x000FFF28 0x000FFF24 0x000FFF20 0x000FFF1C 0x000FFF18 0x000FFF14 0x000FFF10 0x000FFF0C 0x000FFF08 RN 14 (12) (15) 0 1 2 3 10 11 13
Decimal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Hexadecimal 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E
Sound Generator UART 0 RX UART 0 TX UART 1 RX UART 1 TX UART 2 RX UART 2 TX I2C Alarm Comparator RTC (Watchtimer) / Calibration Unit DMA
0x000FFF04 (Continued)
61
MB91360G Series
(Continued)
Interrupt number Interrupt Delayed interrupt activation bit System reserved *3 System reserved Security vector System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by the INT instruction.
*3
Interrupt level *1 Setting Register ICR47 (ICR51) (ICR52) (ICR53) (ICR54) (ICR55) (ICR56) (ICR57) (ICR58) (ICR59) (ICR60) (ICR61) (ICR62) (ICR63) Register address 0x46F 0x473 0x474 0x475 0x476 0x477 0x478 0x479 0x47A 0x47B 0x47C 0x47D 0x47E 0x47F
Interrupt vector *2 Offset 0x300 0x2FC 0x2F8 0x2F4 0x2F0 0x2EC 0x2E8 0x2E4 0x2E0 0x2DC 0x2D8 0x2D4 0x2D0 0x2CC 0x2C8 0x2C4 0x2C0 0x2BC to 0x000 Default Vector address 0x000FFF00 0x000FFEFC 0x000FFEF8 0x000FFEF4 0x000FFEF0 0x000FFEEC 0x000FFEE8 0x000FFEE4 0x000FFEE0 0x000FFEDC 0x000FFED8 0x000FFED4 0x000FFED0 0x000FFECC 0x000FFEC8 0x000FFEC4 0x000FFEC0 0x000FFEBC to 0x000FFC00 RN
Decimal 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
Hexadecimal 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
*1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (0x000FFC00) . The TBR is initialized to this value by a reset.After execution of the internal boot ROM TBR is set to 0x00FFC00. *3 : Used by REALOS *4 : System reserved *5 : Only available on MB91FV360GA *6 : DMA to/from SIO is not yet implemented.
62
MB91360G Series
s PERIPHERAL RESOURCES
1. INSTRUCTION CACHE
This section describes the instruction cache memory included in FR50 Family members and it operation. This only applies to MB91FV360GA and MB91F361GA. (1) General Description The instruction cache is temporary memory. When an external low-speed memory accesses an instruction code, the instruction cache stores the single-accessed code to increase the second and subsequent access speeds.Setting this memory to the RAM mode enables software to directly read and write instruction cache data RAM and tag RAM. (2) Main Body Structure * FR basic instruction length : 2 bytes * Block arrangement system : 2-way set associative system * Block One way consists of 128 blocks. One block consists of 16 bytes ( = 4 sub-blocks) . One sub-block consists of 4 bytes ( = 1 bus access unit) .
4 bytes
4 bytes I3
4 bytes I2
4 bytes I1
4 bytes I0
Way 1 Cache tag 128 blocks Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0
Cache tag
Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0
Block 127
Way 2 Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0
128 blocks Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 127
Instruction Cache Structure
63
MB91360G Series
Way 1 31 Address tag 07 SBV3 SBV2 06 ABV1 05 SBV0 04 TAGV 09 08
Reserved
03
02 LRU
01 ETLK
00
Reserved
Sub-block valid LRU Entry lock Way 2 31 Address tag 07 SBV3 SBV2 06 ABV1 05 SBV0
TAG valid
09
08
Reserved
04 TAGV
03
02
Reserved
01 ETLK
00
Sub-block valid Entry lock
TAG valid
Instruction Cache Tag
64
MB91360G Series
(3) Control Register Structure IRBS (32 bits) Address : 00000300H
31 0 R 23 0 R 30 0 R 22 0 R 29 0 R 21 0 R 28 0 R 20 0 R 27 0 R 19 0 R 26 0 R 18 0 R 25 0 R 17 0 R 24 0 R 16 1 R
Initial value 00000000B
Initial value 00000001B ICR26
15
14 IRBS R/W 6
13 IRBS R/W 5
12 IRBS R/W 4
11 3
10 2
9 1
8 0
Address : 00000302H
IRBS R/W 7
Initial value 0010 - - - -B
Initial value --------B
IRBS [bits 15 to 12] These bits are used to set the base address of cache RAM at access in the RAM mode. Align cache RAM in units of 4 K bytes. These bits are initialized by INIT. The initial value is the 00012000H address. ISIZE (8 bits)
7 6 5 4 3 2 1 SIZE1 R/W 0 SIZE0 R/W
Initial value
00000307H
- - - - - - 11B
The ICHCR (I-CacHe Control Register) controls the instruction cache operations. Writing to the ICHCR does not affect caching of instructions fetched within three subsequent cycles. ICHCR (8 bits) Initial value
7 6 5 GBLK R/W 4 ALFL R/W 3 EOLK R/W 2 ELKR R/W 1 FLSH R/W 0 ENAB R/W
000003E7H
RAM R/W
0 - 000000B
65
MB91360G Series
2. BOOT ROM
The Boot ROM is a fixed start-up routine which is located at FF000 (Reset entry) and will therefore be executed after every RST or INIT. The purpose of this ROM is to configure the device after a reset and to provide a simple serial bootloader for programming the embedded Flash memories. The Boot ROM contains three logical parts : (1) Chip Initializations Immediately after each reset, the following settings will be made : CS0 : 200000...2FFFFF, 32 Bit Bus, 1 wait-state (default external access) CS1 : 180000...1FFFFF, 32 Bit Bus, 1 wait-state (Flash Area only on F361GA) CS7 : 100000...10FFFF, 16 Bit Bus, 1 wait-state (CAN) In addition, the Table-Base Register will be initialized to 1FFC00 (F361GA only) and the synchronous reset (see TBCR) will be enabled. (2) Check for Bootcondition After the chip initialization, the "Security-Vector" will be checked (Vector #66) . The purpose of this feature is to disable the bootstraploader due to security reasons. The RSRR (reset cause register) will be read and saved. If no power-on reset (external INIT input, RSRR = 0x80) is indicated, a branch to the user application will be initiated (Branch to 1F4000) . If INIT was detected and the "Security-Vector" check okay, the following conditions must be met in order to start the Bootstraploader : Within a certain time, the start-up character "V" must be received via UART0 (9600, 8N1) . The time-out is set to 200 ms. (3) Bootstraploader If the Bootcondition was met, an acknowledge character "F" will be transmitted via UART0 to indicate that the Bootloader is ready to accept commands. 4 different commands are possible : Receive and write to a specified memory block Dump the contents of a specified memory block Initiate a "CALL" to a certain location Re-dump a calculated checksum for verification (4) Configuration Register (Mode Register F362MD) This register is used to control which pins of the external bus interface are active, where the pins for the external DMA channel are located and which I2C module is used. address 000001FEH access Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 IICSEL R/W 0
ASYMCLKT HIZ_D_A R/W 0 R/W 0
HIZ_ECLK HIZ_D_23_16 HIZ_D_15_0 DMASWP R/W 0 R/W 0 R/W 0 R/W 0
66
MB91360G Series
3. CLOCK MODULATOR
An important property of MCUs and other electronic devices is their electromagnetic compatibility - EMC. Besides a low susceptibility against external interferences, a low radiated emission is desired to avoid interference of adjacent devices. Particularly the system clock and derived signals such as data- and address busses contribute significantly to the radiated emission. The purpose of the clock modulator is to spread the energy of these signals over a wide range of frequencies and thus reducing the amplitudes of the fundamental and harmonic frequencies. With the use of an advanced frequency modulation algorithm, the Fujitsu built in clock modulator can achieve an attenuation of up to 20-25 dB compared to non modulated clock operation. Since the modulator is highly configurable, it can be optimally adjusted to the actual application in order to achieve minimal electromagnetic interference. By default, the modulator is disabled and the MCU is running with unmodulated clock. If you plan to use this feature, please contact Fujitsu.
67
MB91360G Series
4. I/O PORTS
There are 3 types of I/O port register structure; port data register (PDR7 to PDR5) , data direction register (DDR7 to DDR5) , and portfunction registers (PFR7 to PRF5) , where bits PDR7 to PDR5, bits DDR7 to DDR5, and bits PFR7 to PRF5 correspond respectively. Each bit on the register corresponds to an external pin. The PFR settings define whether a pin is used as a functional I/O (e.g. UART output) or as general purpose pin. * For input (DDR = "0") setting; PDR reading operation : reads level of corresponding external pin. PDR writing operation : writes set value to PDR. * For output (DDR = "1") setting; PDR reading operation : reads PDR value. PDR writing operation : outputs PDR value to corresponding external pin.
68
MB91360G Series
(1) Register configuration Port Data Register bit 7 Address : 00000007H 00000008H 00000009H 0000000BH 00000010H 00000011H 00000012H 00000013H 00000014H 00000015H 00000016H 00000017H 00000018H 00000019H 0000001AH 0000001BH 0000001CH
PDR7
bit 0 Initial value Access 111XXXXXB XXXXXXXXB XXXXXXX1B XXXXXXXXB XXXXXXXXB XXXXXXXXB X - - - X - - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - - XXXXB - -XXXXXXB XXXXXXXXB XXXXXXXXB --XXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PDR8
PDR9
PDRB
PDRG
PDRH
PDRI
PDRJ
PDRK
PDRL
PDRM
PDRN
PDRO
PDRP
PDRQ
PDRR
PDRS
69
MB91360G Series
Data directon Register bit 7 Address : 00000607H 00000608H 00000609H 0000060BH 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH
DDR7
bit 0 Initial value Access 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B - - - - 0 - - -B 00000000B 00000000B 00000000B - - - - 0000B - - 000000B 00000000B 00000000B - - 000000B 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DDR8
DDR9
DDRB
DDRG
DDRH
DDRI
DDRJ
DDRK
DDRL
DDRM
DDRN
DDRO
DDRP
DDRQ
DDRR
0000040CH
DDRS
00000000B
R/W
70
MB91360G Series
Port function registers (PFR) PFR7 Address : 00000617H PFR8 Address : 00000618H PFR9 Address : 00000619H PFRB Address : 0000061BH PFR27 Address : 00000627H PFRG Address : 00000410H PFRH Address : 00000411H PFRI Address : 00000412H PFRJ Address : 00000413H PFRK Address : 00000414H PFRL Address : 00000415H PFRM Address : 00000416H PFRN Address : 00000417H
7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70
Initial value Access 00001111B R/W
7 P87
6 P86
5 P85
4 P84
3 P83
2 P82
1
0
Initial value Access 111110 - -B R/W
7 P97
6 P96
5 P95
4 P94
3 P93
2 P92
1 P91
0 P90
Initial value Access 11110101B R/W
7 PB7
6 PB6
5 PB5
4 PB4
3 PB3
2 PB2
1 PB1
0 PB0
Initial value Access 00000000B R/W
7 P277
6 P276
5 P275
4 P274
3 P273
2 P272
1 P271
0 P270
Initial value Access 1111 - 00 -B R/W
7 PG7
6 PG6
5 PG5
4 PG4
3 PG3
2 PG2
1 PG1
0 PG0
Initial value Access 00000000B R/W
7 PH7
6 PH6
5 PH5
4 PH4
3 PH3
2 PH2
1 PH1
0 PH0
Initial value Access 00000000B R/W
7
6
5
4
3 PI3
2
1
0
Initial value Access - - - - 0 - - -B R/W
7 PJ7
6 PJ6
5 PJ5
4 PJ4
3 PJ3
2 PJ2
1 PJ1
0 PJ0
Initial value Access 00000000B R/W
7 PK7
6 PK6
5 PK5
4 PK4
3 PK3
2 PK2
1 PK1
0 PK0
Initial value Access 00000000B R/W
7 PL7
6 PL6
5 PL5
4 PL4
3 PL3
2 PL2
1 PL1
0 PL0
Initial value Access 00000000B R/W
7
6
5
4
3 PM3
2 PM2
1 PM1
0 PM0
Initial value Access - - - - 0000B R/W
7
6
5 PN5
4 PN4
3 PN3
2 PN2
1 PN1
0 PN0
Initial value Access - - 000000B R/W
(Continued)
71
MB91360G Series
(Continued)
PFRO Address : 00000418H PFRP Address : 00000419H PFRQ Address : 0000041AH PFRR Address : 0000041BH PFRS Address : 0000041CH
7 PO7 6 PO6 5 PO5 4 PO4 3 PO3 2 PO2 1 PO1 0 PO0
Initial value Access 00000000B R/W
7 PP7
6 PP6
5 PP5
4 PP4
3 PP3
2 PP2
1 PP1
0 PP0
Initial value Access 00000000B R/W
7
6
5 PQ5
4 PQ4
3 PQ3
2 PQ2
1 PQ1
0 PQ0
Initial value Access - - 000000B R/W
7 PR7
6 PR6
5 PR5
4 PR4
3 PR3
2 PR2
1 PR1
0 PR0
Initial value Access 00000000B R/W
7 PS7
6 PS6
5 PS5
4 PS4
3 PS3
2 PS2
1 PS1
0 PS0
Initial value Access 00000000B R/W
72
MB91360G Series
5. DMA CONTROLLER (DMAC)
The DMAC module is used to implement direct memory access (DMA) transfer in FR50 series devices. In a DMA transfer controlled by this module, various types of data can be transferred at high speed without involving the CPU, thus increasing system performance. (1) Hardware Configuration The following are the main components of the DMAC module : * Five independent DMA channels * 5-channel independent access control circuit * 32-bit address registers (Reload can be specified : Two registers for each channel.) * 16-bit transfer count registers (Reload can be specified : One register for each channel.) * 4-bit block count registers (One register for each channel) * External transfer request input pins DREQ0, DREQ1, and DREQ2 (only channels 0, 1, and 2) * External transfer request acceptance output pins DACK0, DACK1, and DACK2 (only channels 0, 1, and 2) * DMA termination output pins DEOP0, DEOP1, and DEOP2 (only channels 0, 1, and 2) * Two-cycle transfer (2) Main Functions The following are the main functions of data transfer performed by the module : * Independent data transfer in multiple channels is enabled (5 channels) . a : Priority (channel 0 > channel 1 > channel 2 > channel 3 > channel 4) b : Priority can be alternated between channel 0 and channel 1. c : DMAC start cause * External-only pin input (edge detection/level detection channels 0 to 2 only) * Internal peripheral request (interrupt request is shared, including external interrupts) * Software request (register write) d : Transfer mode * Demand transfer, burst transfer, step transfer, block transfer * Addressing mode 32-bit full address specification (increase, decrease, fixed) (An address increment/decrement size of -255 to +255 can be specified.) * Data types of byte, halfword, and word lengths * Single-shot/reload selectable
73
MB91360G Series
(3) Registers Configuration Channel 0 control/status register A Channel 0 control/status register B Channel 1 control/status register A Channel 1 control/status register B Channel 2 control/status register A Channel 2 control/status register B Channel 3 control/status register A Channel 3 control/status register B Channel 4 control/status register A Channel 4 control/status register B Overall control register Channel 0 transfer source address register Channel 1 transfer source address register Channel 2 transfer source address register Channel 3 transfer source address register Channel 4 transfer source address register
DMACA0 0000200H DMACB0 0000204H DMACA1 0000208H DMACB1 000020CH DMACA2 0000210H DMACB2 0000214H DMACA3 0000218H DMACB3 000021CH DMACA4 0000220H DMACB4 0000224H D M A C R 0000240H
DMASA0 0001000H
Channel 0 transfer destination address register DMADA0 0001004H
DMASA1 0001008H
Channel 1 transfer destination address register DMADA1 000100CH
DMASA2 0001010H
Channel 2 transfer destination address register DMADA2 0001014H
DMASA3 0001018H
Channel 3 transfer destination address register DMADA3 000101CH
DMASA4 0001020H
Channel 4 transfer destination address register DMADA4 0001028H
74
MB91360G Series
(4) Block Diagram
Counter DMA trnasfer request to bus controller Buffer Selector Write back DMA start cause selection circuit and request acceptance control Peripheral start request/stop input
External pin start request/stop input
DTC 2-step register DTCR Counter
DSS [3:0] Buffer Read Write Read/Write control Selector BLK register Status transition circuit Priority circuit To transfer controller ERIR, EDIR Clear peripheral interrupt
TYPE, MOD, WS
IRQ [4:0] MCLREQ
Selector
Bus control section
DDNO
To bus controller
DMA control Counter buffer Selector
DSAD 2-step register
SDAM, SASZ [7:0] SADR
Address counter
Access Address
Write-back
Counter buffer
Selector
DDAD 2-step register
DADM, DASZ [7:0] DADR
Write-back DMAC 5-channel block diagram
Bus control section
DDNO register
X-bus
75
MB91360G Series
6. UART
The UART is a serial I/O port for performing asynchronous (stop-start synchronization) communications. The MB91360G series contains three UART channels. (1) * * * * * * * * Features Full-duplex, double buffering Supports asynchronous (stop-start synchronization) communications Supports multi-processor mode Fully programmable baud rate The baud rate can be set using an internal timer. (See the U-TIMER section.) Supports flexible baud rate setting using an external clock Error detection function (parity, framing, overrun) Non return to zero (NRZ) transfer signal Supports DMA transfer activation using an interrupt
76
MB91360G Series
(2) Register Configuration Register structure
15 SCR SSR ULS 8 bits 8 bits 87 SMR SIDR (R)/SODR (W) 0
Access
R/W R/W
Serial input register (SIDR)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Serial output register (SODR)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Serial status register (SSR)
7 PE 6 ORE 5 FRE 4 RDRF 3 TDRE 2 1 RIE 0 TIE
Serial mode register (SMR)
7 MD1 6 MD0 5 4 3 CS0 2 1 SCKE 0
Serial control register (SCR)
7 PEN 6 P 5 SBL 4 CL 3 A/D 2 REC 1 RXE 0 TXE
UART level select register (ULS)
7 6 5 4 3 NSDO 2 NSDI 1 UTDBL 0 UDBL
SMR
Address Bits 0000 0063H 0000 006FH 0000 007BH Address Bits 0000 0062H 0000 006EH 0000 007AH
7 MD1 R/W 7 PEN R/W
6 MD2 R/W 6 P R/W
5
4
3 CS0 W
2
1
0
Reserved Reserved
Reserved Reserved Reserved
Initial value 00 - - 0 - 00B Access
5 SBL R/W
4 CL R/W
3 A/D R/W
2 REC W
1 RXE R/W
0 TXE R/W
SCR
Initial value 00000100B Access
77
MB91360G Series
(3) Block Diagram
Control signals Reception interrupt (to CPU) SCK (Clock) From U-TIMER Clock selection circuit Receiving clock Transmitting clock Transmission interrupt (to CPU)
Reception control circuit SI (Reception data) Start bit detecter
Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter SO (Transmission data)
Received bit counter Received parity bit counter
Reception status detecton circuit
Reception Shifter Reception completed SIDR
Transmission Shifter Start of transmission SODR
Reception error occurrence signal for DMA (to DMAC)
R - BUS
MD1 MD0 SMR register SCR register
CS0 SCKE SOE
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
78
MB91360G Series
7. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-timer (U-TIMER) is a 16-bit timer used to generate the baud rate for the UART. The operating frequency of the chip and the U-TIMER reload value can be combined to set a user-defined baud rate. The MB91360G series contains three U-TIMER channels. The intervaltimers can count for a maximum of 216 x . (1) Block Diagram
15 UTIMR (reload register)
0
15
Load UTIM (U-timer) Clock
0
(Peripheral clock)
Underflow control
f.f.
To UART
79
MB91360G Series
(2) Register Configuration Register structure
15 87 UTIM UTIMR DRCL UTIMC 0
Access
R W R/W R : Read, W : Write
UTIM Address Bits 0-ch 00000068H 1-ch 00000074H 2-ch 00000080H UTIMR Reload Register UTIMR Address Bits 0-ch 00000068H 1-ch 00000074H 2-ch 00000080H UTIMC Address 0-ch 0000006BH 1-ch 00000077H 2-ch 00000083H
15 b15
14 b14
2 b2
1 b1
0 b0
Initial value Access 0 R
15 b15
14 b14
2 b2
1 b1
0 b0
Initial value Access 0 W
UTIMC U Timer Control Register
7 UCC1 6 5 4 3 2 1 UTST 0 UTCR
Initial value Access 0---0001 R/W
UNDR Reserved
80
MB91360G Series
8. PWM TIMER
The PWM (Pulse Width Modulation) timer can output high-precision pulse waves at an arbitrary cycle and pulse width (duty ratio) . The MB91360G series contains eight PWM timer channels. Each of the channels consists of a 16-bit downcounter, cycle setting register, duty setting register, and pin controller. The control status register for each channel is used to indicate the operation status of the PWM timer. General control registers 1 and 2 are common registers shared by four channels, serving for input and software triggering. (1) Features * The count clock for the 16-bit down-counter can be selected from among the following four types : Internal clocks : , /4, /16, /64 ( : Machine clock for peripherals) * The counter can be initialized to "FFFFH" by a reset or underflow. The 16-bit down-counter causes an underflow when it changes from "0000H" to "FFFFH". * Each channel has PWM outputs. * Eight channels : Eight output pins * Registers * Cycle setting register : Data reload register with buffer * Data transfer from the buffer is performed either when an activation trigger is detected or when the downcounter causes an underflow (cycle match) . The output is inverted at a cycle match. * Duty setting register : Compare register with buffer. * The value set in this register is compared to the counter value. The output is inverted when the values match (duty match) . * Pin control * A duty match causes a reset to "1" (given priority) . * An underflow causes a reset to "0". * The output value fix mode enables output of all "L" or all "H". * The polarity can also be specified. * Interrupt requests can be generated by selecting the following interrupt sources : * Activation of the PWM timer (software trigger or trigger input) * Occurrence of an underflow (cycle match) * Occurrence of a duty match * Occurrence of an underflow (cycle match) or duty match * You can set simultaneous activation of two or more channels using software or another interval timer. You can also set restarting the PWM timer during operation.
81
MB91360G Series
(2) Register Configuration for Channels 1 to 3
Bits 87
GCN10
Address 00000118H 0000011AH PWM timer ch 0 00000120H 00000122H 00000124H 00000126H PWM timer ch 1 00000128H 0000012AH 0000012CH 0000012EH PWM timer ch 2 00000130H 00000132H 00000134H 00000136H PWM timer ch 3 00000138H 0000013AH 0000013CH 0000013EH
15
0 Access R/W
GCN20
Register name General control register 10 Disable/General control register 20
PDBL0
R/W
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch0 timer register ch0 cycle setting register ch0 duty setting register ch0 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch1 timer register ch1 cycle setting register ch1 duty setting register ch1 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch2 timer register ch2 cycle setting register ch2 duty setting register ch2 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch3 timer register ch3 cycle setting register ch3 duty setting register ch3 control status registers
82
MB91360G Series
(3) PWM Timer Registers for Channels 4 to 7
Bits 87
GCN11
Address 0000011CH 0000011EH PWM timer ch 4 00000140H 00000142H 00000144H 00000146H PWM timer ch 5 00000148H 0000014AH 0000014CH 0000014EH PWM timer ch 6 00000150H 00000152H 00000154H 00000156H PWM timer ch 7 00000158H 0000015AH 0000015CH 0000015EH
15
0 Access R/W
GCN21
Register name General control register 11 Disable/General control register 21
PDBL1
R/W
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch4 timer register ch4 cycle setting register ch4 duty setting register ch4 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch5 timer register ch5 cycle setting register ch5 duty setting register ch5 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch6 timer register ch6 cycle setting register ch6 duty setting register ch6 control status registers
PTMR PCSR PDUT PCNH PCNL
R W W R/W
ch7 timer register ch7 cycle setting register ch7 duty setting register ch7 control status registers
83
MB91360G Series
(4) Configuration Diagram of the Entire PWM Timer
Output pins OCPA0 (PWM0) OCPA1 (PWM1)
16-bit reload timer ch0 ch1 General control register 20 Disable register 0 16-bit reload timer ch2 ch3 General control register 21 Disable register 1 General control register 11 (source selection) General control register 10 (source selection)
TRG input PWM timer ch0 TRG input PWM timer ch1 TRG input PWM timer ch2 TRG input PWM timer ch3 TRG input PWM timer ch4 TRG input PWM timer ch5 TRG input PWM timer ch6 TRG input PWM timer ch7
OCPA2 (PWM2)
OCPA3 (PWM3)
OCPA4 (PWM4) OCPA5 (PWM5)
OCPA6 (PWM6)
OCPA7 (PWM7)
(5) Configuration Diagram of PWM Timer 1 ch
Cycle setting register PCSR Prescalar /1 /4 / 16 / 64
Duty setting register PDUT
Clock 16-bit down-counter Start
Load
cmp
Underflow PPG mask
S Peripheral clock () R
Q
PWM output
Inverted bit Enable Edge detection Interrupt selection IRQ (Interrupt request signal)
TRG input (Internal trigger input)
Software trigger
84
MB91360G Series
9. 16-BIT RELOAD TIMER
Each 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, a prescaler for generating the internal count clock, and a control register. The 16-bit reload timer can also activate DMA transfer using interrupts. The MB91360G series contains six 16-bit reload timer channels. (1) 16 bit Reloard Timer Register Configuration Control status register (TMCSR)
15 7 14 6 13 5 12 4 RELD 11 CSL1 3 INTE 10 CSL0 2 UF 9 1 CNTE 8 0 TRG
16-bit timer register (TMR)
15 0
16-bit reload register (TMRLR)
15 0
85
MB91360G Series
(2) Block diagram
16 16-bit reload register
8
Reload RELD 16-bit down-counter UF GATE CSL1 Clock selector CSL0 TRG CNTE OUT CTL. INTE UF IRQ
16 R-BUS
2
21 23 25
Clear prescalar
PWM (Reload timer 0-ch to 3-ch)* A/D (Reaload timer 4-ch)* * Internally connected
Internal clock
86
MB91360G Series
10. BIT SEARCH MODULE
The bit search module searches for a "0", "1", or change-point in the data written to the input register and returns the position of the detected bit. This section describes the data register for detecting zeros (BSD0) , data register for detecting ones (BSD1) , data register for detecting change-points (BSDC) , and detection result register (BSRR) . a : Data register for detecting zeros (BSD0) Address 0000 03F0H b : Date register for detecting ones (BSD1) Address 0000 03F4H c : Data register for detecting change points (BSDC) Address 0000 03F8H d : Detection Result Register (BSRR) Address 0000 03FCH
31 31 31 31
Register structure
0
Initial value Indeterminate
Access W
Register structure
0
Initial value Indeterminate
Access R/W
Register structure
0
Initial value Indeterminate
Access W
Register structure
0
Initial value Indeterminate
Access R
87
MB91360G Series
* Block Diagram of the Bit Search Module
Input latch
Address decoder
Detection mode
D-BUS
One-detect data conversion
Bit search circuit
Search result
88
MB91360G Series
11. 10-BIT A/D CONVERTER (Successive Approximation Conversion Type)
This section provides an overview of the A/D converter, describes the register structure and functions, and describes the operation of the A/D converter. A/D Converter converts analog input voltage into digital values, and provides the following features. * Conversion time : minimum 178 cycles (32 MHz : 5.6 s, 24 MHz : 7.4 s, 16 MHz : 11.2 s) per channel * RC type successive approximation conversion with sample & hold circuit * 10-bit resolution * Program selection analog input from 16 channels * Single conversion mode : conversion of one selected channel * Scan conversion mode : continuous conversion of multiple channels, programmable for up to 16 channels * Single conversion mode : Convert the specified channel once only. * Continuous mode : Repeatedly convert the specified channels. * Stop mode : Convert one channel then temporarily halt until the next activation. (Enables synchronization of the conversion start timing.) A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to memory. * Startup may be by software, external trigger (falling edge) or timer (rising edge)
89
MB91360G Series
15 ADMD
87 ADCH ADCS ADCD ADBL 8 bit 8 bit
0
Channel setting register (ADCH) bit Address : 00009DH Mode register (ADMD) bit Address : 00009CH Control status register (ADCS) bit Address : 00009FH Data register (ADCD) bit Address : 0000A1H bit Address : 0000A0H Disable register (ADBL) bit Address : 0000A3H
15 14 13 12 11 10 9 8 DBL 7 D7 15 6 D6 14 5 D5 13 4 D4 12 3 D3 11 2 D2 10 1 D1 9 D9 0 D0 8 D8 7 BUSY 6 INT 5 INTE 4 PAUS 3 2 1 STRT 0
Reserved
7 ANS3
6 ANS2
5 ANS1
4 ANS0
3 ANE3
2 ANE2
1 ANE1
0 ANE0
15
14
13
12
11 MOD1
10 MOD0
9 STS1
8 STS0
90
MB91360G Series
* Block Diagram
AVCC MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB ANC AND ANE ANF AVRH/AVRL AVSS D/A Converter
Input circuit
Sequential comparison register Comparator Data bus A/D data register ADCD A/D channel setting register A/D mode register ADCH ADMD ADCS A/D control status register Operating clock Prescaler
Sample-and-hold circuit
Trigger activation ATG Timer activation Output of 16-bit reload timer 4 (internal connection) Machine clock ()
Decoder
91
MB91360G Series
12. INTERRUPT CONTROLLER
An interrupt controller controls interrupt acceptance and arbitration processing. Hardware configuration This module consists of the following : * ICR register * Interrupt priority evaluation circuit * Interrupt level and interrupt number (vector) generator * Hold request cancel request generator Major functions This module has the following major functions : * Detecting an NMI request or interrupt request * Priority evaluation (using the level or number) * Transferring the level of the interrupt cause in the evaluation result (to the CPU) * Transferring the number of the interrupt cause in the evaluation result (to the CPU) * Instructing recovery from stop mode due to an NMI or interrupt level other than 11111 (to the CPU) * Generating a hold request cancel request for the bus master
92
MB91360G Series
(1) Register Configuration
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 R 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000440H Address : 00000441H Address : 00000442H Address : 00000443H Address : 00000444H Address : 00000445H Address : 00000446H Address : 00000447H Address : 00000448H Address : 00000449H Address : 0000044AH Address : 0000044BH Address : 0000044CH Address : 0000044DH Address : 0000044EH Address : 0000044FH Address : 00000450H Address : 00000451H Address : 00000452H Address : 00000453H Address : 00000454H Address : 00000455H Address : 00000456H Address : 00000457H Address : 00000458H Address : 00000459H Address : 0000045AH Address : 0000045BH Address : 0000045CH Address : 0000045DH Address : 0000045EH Address : 0000045FH

ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
(Continued)
93
MB91360G Series
(Continued)
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 R 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000460H Address : 00000461H Address : 00000462H Address : 00000463H Address : 00000464H Address : 00000465H Address : 00000466H Address : 00000467H Address : 00000468H Address : 00000469H Address : 0000046AH Address : 0000046BH Address : 0000046CH Address : 0000046DH Address : 0000046EH Address : 0000046FH

ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Address : 00000045H
MHALTI R/W
LVL4 R
LVL3 R/W
LVL2 R/W
LVL1 R/W
LVL0 R/W
HRCL
94
MB91360G Series
(2) Block Diagram
UNMI
WAKEUP (1 if LEVEL = 11111)
Priority evaluation 5 NMI processing HLDREQ withdrawal request MHALT1 LEVEL4 to 0
NMIRQ (NMI request)
LEVEL evaluation R100 ICR00 VECTOR evaluation R147 (DLYIRQ) ICR47 6
LEVEL and VECTOR generation
VCT5 to 0
R-BUS
95
MB91360G Series
13. EXTERNAL INTERRUPT/NMI CONTROL BLOCK
The external interrupt/NMI controller controls external interrupt requests input from the NMI and INT0 to INT7 pins. Detection of "H" levels, "L" levels, rising edges, or falling edges can be selected (except for the NMI) . The external interrupt/NMI controller can also be used for DMA requests. This section lists the registers of the controller and provides its block diagram. (1) Register configuration of the External Interrupt NMI Controller External interruption permission register (ENIR) Bit
7 EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0
External interruption factors register (EIRR) Bit
15 ER7 14 ER6 13 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0
Request level setting register (ELVR) Bit
15 LB7 14 LA7 6 LA3 13 LB6 5 LB2 12 LA6 4 LA2 11 LB5 3 LB1 10 LA5 2 LA1 9 LB4 1 LB0 8 LA4 0 LA0
Bit
7 LB3
(2) Block diagram
R bus 8 Enable interrupt request register 9 Interrupt request 8 Gate Request F/F 9
Edge detect circuit
INT0 to 7 NMI
External interrupt request register
8 External level register
96
MB91360G Series
14. DELAYED INTERRUPT
Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) is a delayed interrupt generator register and is used to generate the task switching interrupt. Structure of the DICR Address 00000044H Bits
7 6 5 4 3 2 1 0 DLYI R/W
Initial value -------0 Access
97
MB91360G Series
15. CLOCK GENERATION
The MB91V360 generates internal operating clocks as follows : * Base clock generation : Device scales clock source input by 2 (X clock) or oscillates base clock with PLL to generate basic clock (PLL clock) * Generation of each internal clock : Device scales base clock to generate clocks supplied to each block Generation and control of each clock are explained below. Some devices allow the operation of the RTC module based on a separate 32 kHz subclock. See the section about subclock operation for more details. (1) Register Configuration RSRR : Reset Source Register, Watchdog Timer Control Register bit address : 00000480H access Initial Value (INIT) Initial Value (INIT) Initial Value (RST) After Boot ROM ** * : varies with reset factor x : not initialized ** : After execution of the program in the internal boot ROM the reset source is visible
15 INIT R 1 * X 0 14 HSTB R 0 * X 0 13 WDOG R 0 * X 0 12 ERST R 0 X * 0 11 SRST R 0 X * 0 10 0 9 WT1 R/W 0 0 0 0 8 WT0 R/W 0 0 0 0
STCR : Standby Control Register
bit address : 00000481H access Initial Value (INIT) Initial Value (HST) * Initial Value (INIT) Initial Value (RST)
7 STOP R/W 0 0 0 0 6 SLEEP R/W 0 0 0 0 5 HIZ R/W 1 1 1 X 4 SRST R/W 1 1 1 1 3 OS1 R/W 0 1 X X 2 OS0 R/W 0 1 X X 1 0 OSCD2 OSCD1 R/W 1 1 1 X R/W 1 1 1 X
* : Valid only when this initialization is performed simultaneously with initialization by INIT : others same as INIT.
(Continued)
98
MB91360G Series
TBCR : Time-based counter control register bit address : 00000482H Initial Value (INIT) Initial Value (RST)
15 TBIF 0 0 R/W 14 TBIE 0 0 R/W 13 TBC2 X X R/W 12 TBC1 X X R/W 11 TBC0 X X R/W 10 X X R/W 9 8 SYNCR SYNCS 0 X R/W 0 X R/W
CTBR : Time-based counter clear register bit address : 00000483H Initial Value (INIT) Initial Value (RST)
7 D7 X X W 6 D6 X X W 5 D5 X X W 4 D4 X X W 3 D3 X X W 2 D2 X X W 1 D1 X X W 0 D0 X X W
CLKR : Clock source control register
15 14 13 12 11 10 9 8 bit address : 00000484H PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0
Initial Value (INIT) Initial Value (RST)
R/W 0 X
R/W 0 X
R/W 0 X
R/W 0 X
R/W 0 X
R/W 0 X
R/W 0 X
R/W 0 X
WPR Watchdog reset generation postponement register bit address : 00000485H Initial Value (INIT) Initial Value (RST)
7 D7 R/W X X 6 D6 R/W X X 5 D5 R/W X X 4 D4 R/W X X 3 D3 R/W X X 2 D2 R/W X X 1 D1 R/W X X 0 D0 R/W X X
DIVR0 : Base clock division setting register 0 bit address : 00000486H Initial Value (INIT) Initial Value (RST)
7 B3 R/W 0 X 6 B2 R/W 0 X 5 B1 R/W 0 X 4 B0 R/W 0 X 3 P3 R/W 0 X 2 P2 R/W 0 X 1 P1 R/W 1 X 0 P0 R/W 1 X
DIVR1 : Base clock division setting register 1 bit address : 00000487H Initial Value (INIT) Initial Value (RST)
7 T3 R/W 0 X 6 T2 R/W 0 X 5 T1 R/W 0 X 4 T0 R/W 0 X 3 S3 R/W 0 X 2 S2 R/W 0 X 1 S1 R/W 0 X 0 S0 R/W 0 X
(Continued)
99
MB91360G Series
(Continued)
CMCR : Clock Control for CAN Modules address 0164H address 0165H
bit 15 PRE7 bit 14 PRE6 bit 13 PRE5 bit 12 PRE4 bit 11 PRE3 bit 10 PRE2 bit 9 PRE1 bit 8 PRE0
initial 11111111 initial 00000000
bit 7 PRES
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Subclock RTC32 (CLKR2) This register is used to control the RTC32 mode bit for use in subclock system. address 000046H access initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 R/W 0 bit 9 R/W 0 bit 8 RTC32 R/W 0
100
MB91360G Series
(2) Block Diagram
R B U S
DIVR0 and DIVR1 registers
[Clock generation block]
CPU clock division CPU clock CLKB Resource clock CLKP Ext. bus clock CLKT MONCLK Clock for CAN CANCLK Stop control
Resource clock division
Ext. bus clock division CLKR register SELCLK X0 X1 Oscillator circuit 4 MHz 1 0 X0A X1A Oscillator circuit 32 kHz STCR register internal Interrrupt internal Reset State transition control circuit PLL1 1/2 Clock mod
Clock for RTC
[Stop/sleep control block] Stop state Sleep state Reset occurrence F/F Reset occurrence F/F [Reset source circuit] Internal reset (RST) Internal reset (INIT)
HST
RST INIT RSRR register
WPR register
Watchdog F/F Timer-base counter
CTBR register
TBCR register
Overflow detect. F/F Time-base timer interrupt request [Watchdog control block]
Interrupt enable
101
MB91360G Series
16. BUS INTERFACE
The external bus interface controls the interfaces with the external memory and external I/Os. * Up to 32-bit (4 GB) address output. * Up to eight independent banks provided by chip-select function The banks can be set in 64-KB (minimum) at any position in the logic address space. Can be set to no area * 32/16/8 bit bus width setup can be performed for each chip-select area. * Programmable automatic memory wait (up to 7 cycles) insertion Note : Chip Select Areas CS7 and CS1 are used for the internal CAN modules and Flash module (F361GA only) respectively. The necessary register settings are done by an internal boot routine. Take care not to overwrite register bits related to those CS areas. If the CAN macros and the flash memory which are connected internally to the external bus (also called User Logic Bus) are used, a certain number of data, address and control ports of the external bus interface cannot be configured as general purpose IO ports. (1) Register Configuration Area select Registers (ASR0 to ASR7) bit 7 00000640H 00000644H 00000648H 0000064CH 0000650H 00000654H 00000658H 0000065CH
ASR0
bit 0 00000000B 0000XXXXB 0000XXXXB 0000XXXXB 0000XXXXB 0000XXXXB 0000XXXXB 00000000B
R/W W W W W W W W W
ASR1
ASR2
ASR3
ASR4
ASR5
ASR6
ASR7
After execution of the code internal boot ROM ASR0 is set to "0x20", ASR1 to "0x1C", and ASR7 to "0x10" (F361GA only)
(Continued)
102
MB91360G Series
(Continued)
Area Mask Register (AMR0 to AMR7) AMR0 00000642H AMR1 00000646H AMR2 0000064AH AMR3 0000064EH AMR4 0000652H
AM R0
FFFFFFFFH 0000XXXXH 0000XXXXH 0000XXXXH 0000XXXXH 0000XXXXH 0000XXXXH 00000000H
W W W W W W W W
AMR1
AMR2
AMR3
AMR4
AMR5 00000656H AMR6 0000065AH AMR7 0000065CH Area Mode Registers (AMD0 to AMD7) 00000660H
RDYE BW1
AMR5
AMR6
AMR7
BW0
WTC2
WTC1
WTC0
00000111B
R/W
CHE (CacHe Enable register) 00000670H
CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0
11111111B
R/W
CSE (Chip Select Enable register) 00000668H
CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0
00000001B
R/W
103
MB91360G Series
(2) Block Diagram
ADDRESS BUS DATA BUS A-OUT 32 32 EXTERNAL DATA BUS write bus switch MUX
read buffer
switch
DATA BLOCK ADDRESS BLOCK
+1 or +2
EXTERNAL ADDRESS BUS
address buffer
ASR ASZ comparator
CS0 to CS7
External pin control section All block control resisters & control
RD WR0, WR1 WR2, WR3 BRQ BGRNT RDY CLK
104
MB91360G Series
17. CAN CONTROLLER
This section provides an overview of the CAN Interface, describes the register structure and functions, and describes the operation of the CAN Interface. The CAN controller is a module built into a MB91360G series. The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. The CAN controller has the following features : * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Supports full-bit comparison, full-bit mask and partial bit mask filtering. - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz) The following sections only describe CAN 0. For the addresses of the registers of the other CAN channels see the IO-Map.
105
MB91360G Series
(1) List of Control Registers List of Control Registers (1) Address CAN0 100000H 100001H 100002H 100003H 100004H 100005H 100006H 100007H 100008H 100009H 10000AH 10000BH 10000CH 10000DH 10000EH 10000FH 100010H 100011H 100012H 100013H 100014H 100015H 100016H 100017H 100018H 100019H Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Abbreviation BVALR0 TREQR0 TCANR0 TCR0 RCR0 RRTRR0 ROVRR0 RIER0 CSR0 LEIR0 RTEC0 BTR0 IDER0 Access R/W R/W W R/W R/W R/W R/W R/W R/W, R R/W R R/W R/W Initial Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00 - - - 000 0 - - - - 0 - 1 - - - - - - - - 000 - 0000 00000000 00000000 -1111111 11111111 XXXXXXXX XXXXXXXX
106
MB91360G Series
List of Control Registers (2) Address CAN0 10001AH 10001BH 10001CH 10001DH 10001EH 10001FH 100020H 100021H 100022H 100023H 100024H 100025H 100026H 100027H 100028H 100029H 10002AH 10002BH Acceptance mask register 1 AMR10 R/W XXXXX - - - XXXXXXXX Acceptance mask register 0 AMR00 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask select register AMSR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation TRTRR0 RFWTR0 TIER0 Access R/W R/W R/W Initial Value 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX
107
MB91360G Series
(2) Message Buffers List of Message Buffers (ID Registers) (1) Address CAN0 10002CH to 10004BH 10004CH 10004DH 10004EH 10004FH 100050H 100051H 100052H 100053H 100054H 100055H 100056H 100057H 100058H 100059H 10005AH 10005BH 10005CH 10005DH 10005EH 10005FH 100060H 100061H 100062H 100063H 100064H 100065H 100066H 100067H ID register 6 IDR60 R/W XXXXX - - - XXXXXXXX ID register 5 IDR50 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR40 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR30 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR20 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR10 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR00 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX
General-purpose RAM
R/W
108
MB91360G Series
List of Message Buffers (ID Registers) (2) Address CAN0 100068H 100069H 10006AH 10006BH 10006CH 10006DH 10006EH 10006FH 100070H 100071H 100072H 100073H 100074H 100075H 100076H 100077H 100078H 100079H 10007AH 10007BH 10007CH 10007DH 10007EH 10007FH 100080H 100081H 100082H 100083H 100084H 100085H 100086H 100087H ID register 14 IDR14 R/W XXXXX - - - XXXXXXXX ID register 13 IDR13 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR90 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 8 IDR80 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX ID register 7 IDR70 R/W XXXXX - - - XXXXXXXX XXXXXXXX XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXX
109
MB91360G Series
List of Message Buffers (ID Registers) (3) Address CAN0 100088H 100089H 10008AH 10008BH ID register 15 IDR15 R/W XXXXX - - - XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXX
List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN0 10008CH 10008DH 10008EH 10008FH 100090H 100091H 100092H 100093H 100094H 100095H 100096H 100097H 100098H 100099H 10009AH 10009BH 10009CH 10009DH 10009EH 10009FH 1000A0H 1000A1H Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 Abbreviation DLCR00 DLCR10 DLCR20 DLCR30 DLCR40 DLCR50 DLCR60 DLCR70 DLCR80 DLCR90 DLCR100 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX
110
MB91360G Series
List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN0 1000A2H 1000A3H 1000A4H 1000A5H 1000A6H 1000A7H 1000A8H 1000A9H 1000AAH 1000ABH 1000ACH to 1000B3H 1000B4H to 1000BBH 1000BCH to 1000C3H 1000C4H to 1000CBH 1000CCH to 1000D3H 1000D4H to 1000DBH 1000DCH to 1000E3H 1000E4H to 1000EBH 1000ECH to 1000F3H 1000F4H to 1000FBH Register DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR110 DLCR120 DLCR130 DLCR140 DLCR150 Access R/W R/W R/W R/W R/W Initial Value - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX - - - - XXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX 111
Data register 0 (8 bytes)
DTR00
R/W
Data register 1 (8 bytes)
DTR10
R/W
Data register 2 (8 bytes)
DTR20
R/W
Data register 3 (8 bytes)
DTR30
R/W
Data register 4 (8 bytes)
DTR40
R/W
Data register 5 (8 bytes)
DTR50
R/W
Data register 6 (8 bytes)
DTR60
R/W
Data register 7 (8 bytes)
DTR70
R/W
Data register 8 (8 bytes)
DTR80
R/W
Data register 9 (8 bytes)
DTR90
R/W
MB91360G Series
List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN0 1000FCH to 100103H 100104H to 10010BH 10010CH to 100113H 100114H to 10011BH 10011CH to 100123H 100124H to 10012BH Register Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
Data register 10 (8 bytes)
DTR100
R/W
Data register 11 (8 bytes)
DTR110
R/W
Data register 12 (8 bytes)
DTR120
R/W
Data register 13 (8 bytes)
DTR130
R/W
Data register 14 (8 bytes)
DTR140
R/W
Data register 15 (8 bytes)
DTR150
R/W
Configuration Register (CREG) Address Register CAN0 10012CH 10012DH Configuration register CREG0 R/W 00000000 00000110 Abbreviation Access Initial Value
112
MB91360G Series
(3) Block Diagram
CREG
CANCLK CLKT
Clock Configuration
Clock for CAN transmit/receive operation Clock for External Bus Access TQ (Operating clock) SYNC, TSEG1, TSEG2
External Bus (User Logic Bus) PSC PR PH RSJ TOE TS RS CSR HALT NIE NT NS1,0 BTR RTEC BVALR TREQR
Prescaler 1 to 64 frequency division
Bit timing generation
Node status change interrupt generation
Node status change interrupt Error control
Bus state machine
IDLE, INT, SUSPND, transmit, receive, ERR, OVRLD
TBFx, clear
Transmitting/ receiving sequencer Transmitting buffer x decision TBFX Data Acceptance counter filter control TDLC RDLC IDSEL
Error frame generation Overload frame generation ARBLOST Output driver TX
TBFX TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 IDR0 to 15, DLCR0 to 15, DTR0 to 15, RAM LEIR 0 1 TBFx, set, clear Transmission complete interrupt generator RBFx, set Reception complete interrupt generation RBFx, TBFx, set, clear RBFx, set IDSEL Reception completed interrupt Transmission complete interrupt
BITER, STFER, CRCER, FRMER, ACKER Transmission shift register
Stuffing CRC ACK
TDLC
generation generation
CRCER RDLC CRC generator/ error check STFER
Receive shift register
Destuffing/ stuffing error check Arbitration check Bit error check Acknowledgment error check Form error check
ARBLOST BITER ACKER FRMER
Acceptance filter
Receiving buffer x decision RBFX
PH1 Input latch
RX
RAM address generation
RBFX, TBFX, RDLC, TDLC, IDSEL
113
MB91360G Series
18. D/A CONVERTER
This section provides an overview of the D/A converter, describes the register structure and functions, and describes the operarton of D/A converter.This block is an R-2R format D/A converter, having ten-bit resolution. The D/A converter has two channels.Output control can be performed independently for the two channels using the D/A control register. (1) Block Diagram
R-Bus
DA DA DA DA DA DA DA DA DA DA 19 18 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA DA DA 09 08 07 06 05 04 03 02 01 00
DVR DA19 2R DA18 2R DA17 R DA09
DVR
2R DA08 2R DA07
R
R
R
DA11 2R DA10 R
DA01 2R DA00 R
2R 2R DAE1 Standby control
2R 2R DAE0 Standby control
DA output ch1
DA output ch0
114
MB91360G Series
(2) Registers D/A control register (DACR) bit Address : 0000A5H
7 6 5 4 3 2 MODE 1 DAE1 0 DAE0
D/A converter data register (ch 0) (DADR0) bit Address : 0000A6H bit Address : 0000A7H
15 7 DA07 14 6 DA06 13 5 DA05 12 4 DA04 11 3 DA03 10 2 DA02 9 DA09 1 DA01 8 DA08 0 DA00
D/A converter data register (ch 1) (DADR1) bit Address : 0000A8H bit Address : 0000A9H D/A clock control (DDBL) bit Address : 0000ABH
7 6 5 4 3 2 1 0 DBL 15 7 DA17 14 6 DA16 13 5 DA15 12 4 DA14 11 3 DA13 10 2 DA12 9 DA19 1 DA11 8 DA18 0 DA10
115
MB91360G Series
19. 100 kHz I2C INTERFACE
This section describes the functions and operation of the MB91360G series basic I2C interface. This interface allows operation up to 100 kHz and 8-bit-addressing. The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus. (1) I2C Interface Features The MB91360G series microcontroller includes a built-in one-channel I2C interface. The I2C interface has the following features. * Master/slave sending and receiving functions * Arbitration function * Clock synchronization function * Slave address/general call address detection function * Transfer direction detection function * Repeated start condition generation and detection function * Bus error detection function
116
MB91360G Series
(2) I2C Interface Registers a : Bus Status Register (IBSR)
7 6 RSC (R) (0) 5 AL (R) (0) 4 LRB (R) (0) 3 TRX (R) (0) 2 AAS (R) (0) 1 GCA (R) (0) 0 FBT (R) (0)
Bit no.
Address : 000095H Read/write Default value
BB (R) (0)
b : Bus Control Register (IBCR)
15 14 BEIE (R/W) (0) 13 SCC (R/W) (0) 12 MSS (R/W) (0) 11 ACK (R/W) (0) 10 GCAA (R/W) (0) 9 INTE (R/W) (0) 8 INT (R/W) (0)
Bit no.
Address : 000094H Read/write Default value
BER (R/W) (0)
c : Clock control register (ICCR)
7 6 () () 5 EN (R/W) (0) 4 CS4 (R/W) (X) 3 CS3 (R/W) (X) 2 CS2 (R/W) (X) 1 CS1 (R/W) (X) 0 CS0 (R/W) (X)
Bit no.
Address : 000097H Read/write Default value d : Address Register (IADR)
() ()
15
14 A6 (R/W) (X)
13 A5 (R/W) (X)
12 A4 (R/W) (X)
11 A3 (R/W) (X)
10 A2 (R/W) (X)
9 A1 (R/W) (X)
8 A0 (R/W) (X)
Bit no.
Address : 000096H Read/write Default value e : Data Register (IDAR)
() ()
7
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
Bit no.
Address : 000099H Read/write Default value
D7 (R/W) (X)
f : Clock Disable Register (IDBL)
7 6 () () 5 () () 4 () () 3 () () 2 () () 1 () () 0 DBL (R/W) (0)
Bit no.
Address : 00009BH Read/write Default value
() ()
117
MB91360G Series
(3) I2C Interface Block Diagram
ICCR EN I2C enable 5 Clock divider 1 6 7 8 Clock selector 1 Clock divider 2 2 4 8 16 32 64 128 Clock selector 2 Shift clock edge conversion timing Bus busy Repeat start Last Bit Send/receive First Byte Start-stop condition deector Error Clock signal for division
ICCR CS4 CS3 CS2 CS1 CS0
256
Sync
Shift clock generator
IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE Interrupt request INTE R-bus INT IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable Start-stop condition detector End
Arbitration lost detectior SCL
SDA
IDAR IBSR AAS GCA Slave Global call Slave address comparator
IADR
118
MB91360G Series
20. 400 kHz I2C INTERFACE
This section describes the functions and operation of the fast I2C interface. The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus. (1) * * * * * * * * * * * * * * * * * Features Master/slave transmitting and receiving functions Arbitration function Clock synchronization function General call addressing support Transfer direction detection function Repeated start condition generation and detection function Bus error detection function 7 bit addressing as master and slave 10 bit addressing as master and slave Possibility to give the interface a seven and a ten bit slave address Acknowledging upon slave address reception can be disabled (Master-only operation) Address masking to give interface several slave addresses (in 7 and 10 bit mode) Up to 400 KBit transfer rate Possibility to use built-in noise filters for SDA and SCL Can receive data at 400 KBit if R-Bus-Clock is higher than 6 MHz regardless of prescaler setting Can generate MCU interrupts on transmission and bus error events Supports being slowed down by a slave on bit and byte level
The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400 KBit datarate if the R-Bus-Clock (CLKP) is higher than 6 MHz regardless of the prescaler setting. However, clock stretching on byte level is performed since SCL is pulled low during an interrupt (INT = "1" in IBCR register) .
119
MB91360G Series
(2) Block Diagram
IDBL DBL ICCR 5 CS4 CS3 CS2 CS1 CS0 5 Clock Selector Clock Divider 2 (by 12) SCL Duty Cycle Generator Bus busy Repeat start Last Bit Send/receive Address Data Arbitration Loss Detector ICCR NSF enable SCL Noise Filter SDA Bus Observer Bus Error Sync Clock disable R-Bus Clock (CLKP) FB59 Module Clock Supply
Clock Divider 1 2345
32
Shift Clock Generator
IBSR BB RSC LRB TRX ADT AL IBCR BER BEIE INTE INT R-bus IBCR SCC MSS ACK GCAA 8 IDAR IBSR AAS GCA ISMK ENSB ITMK ENTB RAL enable 10 bit mode received ad. length 10 ITBA 10 10 ITMK 10 7 ISBA 7 ISMK enable 7 bit mode Slave General call Slave Address Comparator 8 Start Master ACK enable ACK Generator GC-ACK enable Start-Stop Condition Generator Interrupt Request MCU IRQ
SCL SDA
120
MB91360G Series
(3) I2C Interface Registers a : Bus Control Register (IBCR2)
15 14 BEIE (R/W) (0) 13 SCC (W) (0) 12 MSS (R/W) (0) 11 ACK (R/W) (0) 10 GCAA (R/W) (0) 9 INTE (R/W) (0) 8 INT (R/W) (0)
Bit no.
Address : 000184H Read/write Default value
BER (R/W) (0)
b : Bus Status Register (IBSR2)
7 6 RSC (R) (0) 5 AL (R) (0) 4 LRB (R) (0) 3 TRX (R) (0) 2 AAS (R) (0) 1 GCA (R) (0) 0 FBT (R) (0)
Bit no.
Address : 000185H Read/write Default value
BB (R) (0)
c : Ten Bit slave Address register (ITBAH, ITBAL) Ten Bit Address high byte
15 14 () (0) 13 () (0) 12 () (0) 11 () (0) 10 () (0) 9 TA9 (R/W) (0) 8 TA8 (R/W) (0)
Bit no.
Address : 000186H Read/write Default value Ten Bit Address low byte
() (0)
7
6 TA6 (R/W) (0)
5 TA5 (R/W) (0)
4 TA4 (R/W) (0)
3 TA3 (R/W) (0)
2 TA2 (R/W) (0)
1 TA1 (R/W) (0)
0 TA0 (R/W) (0)
Bit no.
Address : 000187H Read/write Default value
TA7 (R/W) (0)
d : Ten bit slave address Mask register (ITMKH, ITMKL) Ten Bit Address Mask high byte
15 14 RAL (R) (0) 13 () (1) 12 () (1) 11 () (1) 10 () (1) 9 TM9 (R/W) (1) 8 TM8 (R/W) (1)
Bit no.
Address : 000188H Read/write Default value
ENTB (R/W) (0)
Ten Bit Address Mask low byte
7 6 TM6 (R/W) (1) 5 TM5 (R/W) (1) 4 TM4 (R/W) (1) 3 TM3 (R/W) (1) 2 TM2 (R/W) (1) 1 TM1 (R/W) (1) 0 TM0 (R/W) (1)
Bit no.
Address : 000189H Read/write Default value
TM7 (R/W) (1)
e : Seven Bit slave Address register (ISBA)
7 6 SA6 (R/W) (0) 5 SA5 (R/W) (0) 4 SA4 (R/W) (0) 3 SA3 (R/W) (0) 2 SA2 (R/W) (0) 1 SA1 (R/W) (0) 0 SA0 (R/W) (0)
Bit no.
Address : 00018BH Read/write Default value
() (0)
(Continued)
121
MB91360G Series
(Continued)
f : Seven bit slave address Mask register (ISMK)
15 14 SM6 (R/W) (1) 13 SM5 (R/W) (1) 12 SM4 (R/W) (1) 11 SM3 (R/W) (1) 10 SM2 (R/W) (1) 9 SM1 (R/W) (1) 8 SM0 (R/W) (1)
Bit no.
Address : 00018AH Read/write Default value
ENSB (R/W) (0)
g : Data Register (IDARH, IDAR2) Data register high byte
15 14 () (0) 13 () (0) 12 () (0) 11 () (0) 10 () (0) 9 () (0) 8 () (0)
Bit no.
Address : 00018CH Read/write Default value Data register
() (0)
7
6 D6 (R/W) (0)
5 D5 (R/W) (0)
4 D4 (R/W) (0)
3 D3 (R/W) (0)
2 D2 (R/W) (0)
1 D1 (R/W) (0)
0 D0 (R/W) (0)
Bit no.
Address : 00018DH Read/write Default value
D7 (R/W) (0)
h : Clock control register (ICCR2)
15 14 NSF (R/W) (0) 13 EN (R/W) (0) 12 CS4 (R/W) (1) 11 CS3 (R/W) (1) 10 CS2 (R/W) (1) 9 CS1 (R/W) (1) 8 CS0 (R/W) (1)
Bit no.
Address : 00018EH Read/write Default value
() (0)
i : Clock Disable Register (IDBL2)
7 6 () (0) 5 () (0) 4 () (0) 3 () (0) 2 () (0) 1 () (0) 0 DBL (R/W) (0)
Bit no.
Address : 00018FH Read/write Default value
() (0)
122
MB91360G Series
21. 16-BIT I/O TIMER
The MB91360G Series contains two 16-bit free-running timer modules, two output compare modules, and two input capture modules and supports four input channels and four output channels. The following sections only describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1. The remaining modules have the identical functions and the register addresses should be found in the I/O map. (1) Function Overview a : 16-bit free-running timer The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from this timer counter are used as the base timer for input capture and output compare. * Four counter clocks are available. Internal clock : /4, /16, /32, /64 * An interrupt can be generated upon a counter overflow or a match with compare register 0. * The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare register 0. b : Output compare (2 channels per one module) The output compare module consists of two 16-bit compare registers, compare output latch, and control register. When the 16-bit free-running timer value matches the compare register value, the output level is reversed and an interrupt is issued. * The two compare registers can be used independently. Output pins and interrupt flags corresponding to compare registers * Output pins can be controlled based on pairs of the two compare registers. Output pins can be reversed by using the two compare registers. * Initial values for output pins can be set. * Interrupts can be generated upon a compare match. c : Input capture (2 channels per one module) The input capture module consists of two 16-bit capture registers and control registers corresponding to two independent external input pins. The 16-bit free-running timer value can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin. * The detection edge of an external input signal can be specified. Rising, falling, or both edges * Two input channels can operate independently. * An interrupt can be issued upon a valid edge of an external input signal.
123
MB91360G Series
(2) Registers a : 16-bit free-running timer
15 0000C8H 0000CBH
TCDT
0 Timer data register
TCCS
Timer status register
b : 16-bit output compare
15 0000BCH 0000BEH 0000B8H
OCS1 OCCP0/1
0 Compare register
OCS0
Control status register
c : 16-bit input capture
15 0000B0H 0000B2H 0000ACH
IOTDBL0 IPC0/1
0 Capture register
ICS0/1
Disable/Control status register
(3) Block Diagram
Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Compare register 0 Bus Output compare 1 Compare register 1 TQ OUT1 TQ OUT0 To each block Edge selection
Input caputure 0 Capture register 0 Input caputure 1 Capture register 1 Edge selection IN1 IN0
124
MB91360G Series
22. ALARM COMPARATOR
This section provides an overview of the Alarm Comparator (Also called Under/Overvoltage Detection) , describes the register structure and functions, and describes the operation of the Alarm Comparator. (1) Block Diagram
Alarm comparator - analog part AVDD
Alarm comparator - digital part FR51 RB [15:0] OUT1 DQ CK PD ACSR B0DX RB [15:0] STOP DEC RSLEEP RST CLKP REG CDBLE Interrupt logic F-MODULE IRQ_AC B-MODULE IRQ_AC
ALARM
STOP WRCR PMWR RDCR RSLEEP RST CLKP CDBLE
OUT2
DQ CK CLKP
UMQA02
(2) Registers Alarm Comparator Clock Disable Register (ACCDBL) Address 00000180H Bits
7 6 5 4 3 2 1 0 CDBLE R/W
Initial value - - - - - - - 0B Access Initial value -11xxx00B Access
Alarm Comparator Status Disable Register (ACSR) Address 00000181H Bits
7 6 5 4 OUT2 R 3 OUT1 R 2 IRQ R/W 1 IEN R/W 0 PD R/W OV_EN UV-EN R/W R/W
125
MB91360G Series
23. POWER DOWN RESET
This section provides an overview of the Power Down Reset, describes the register structure and functions, and describes the operation of the Power Down Reset Module. The power down reset module performs a system reset when VCC goes below a threshold voltage. The reset signal is be disabled and enabled by setting the power down reset control register PDRCR. For low power applications the digital and the analog part of the power down reset control circuit can be disabled. (1) Block Diagram
input stage PDCOMP IN OUT EN
RST 9-bit LFSR counter CLR READY
PDRST
S WR RB [1] (RD bit) R
Q
(2) Register
7 6 X 5 X 4 X 3 X 2 CDSBLE R/W 0 X 1 PD R/W 0 X 0 EN R/W 0 X
PDRCR access initial value (INIT) initial value (RST)
X
126
MB91360G Series
24. SERIAL I/O INTERFACE (SIO)
This section provides an overview of the Serial I/O Interface (SIO) , describes the register structure and functions, and describes the operation of the SIO. (1) Block Diagram This block is a serial I/O interface that allows data transfer using clock synchronization. The interface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB. MB91360G series contains two Serial I/O units SIO0 and SIO1. This section only describes SIO0. Please see the IO-Map for the register addresses of SIO1. The serial I/O interface operates in two modes : * Internal shift clock mode : Data is transferred in synchronization with the internal clock. * External shift clock mode : Data is transferred in synchronization with the clock supplied via the external pin (SCK) . By manipulating the general-purpose port sharing the external pin (SCK) , data can also be transferred by a CPU instruc tion in this mode.
Internal data bus
(MSB first) D7 to D0 SIN3 SDR (Serial data register)
D7 to D0 (LSB first) Transfer direction selection Read Write
SOT3
SCK3 Control circuit Shift clock counter
Internal clock
2 SMD2
1 SMD1
0 SMD0 SIE SIR BUSY STOP STRT MODE BDS SCOE
Interrupt request Internal data bus
127
MB91360G Series
(2) Registers Serial mode control status register (SMCS)
15 14 SMD1 13 SMD0 12 SIE 11 SIR 10 BUSY 9 STOP 8 STRT
Address : 000084H
SMD2
7
6
5
4
3 MODE
2 BDS
1
0 SCOE
Address : 000085H
SIO edge selection/clock disable register (SES)
15 14 13 12 11 10 9 DBL 8 NEG
Address : 000086H Serial data register (SDR)
7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0
Address : 000087H
D7
128
MB91360G Series
25. SOUND GENERATOR
This section provides an overview of the Sound Generator, describes the register structure and functions, and describe the operation of the Sound Generator. The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register, Decrement Grade register, Tone Count register, Sound Disable register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter. (1) Registers Sound Control register (SGCR)
7 6 S0 (R/W) (0) 14 () () 5 TONE (R/W) (0) 13 () () 4 () () 12 () () 3 () () 11 () () 2 INTE (R/W) (0) 10 () () 1 INT (R/W) (0) 9 BUSY (R) (0) 0 ST (R/W) (0) 8 DEC (R/W) (0)
Bit no.
Address : 0000EFH Read/write Default value Address : 0000EEH Read/write Default value
S1 (R/W) (0) 15 TST (R/W) (0)
Bit no.
Frequency Data register (SGFR)
7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X)
Bit no.
Address : 0000F1H Read/write Default value
D7 (R/W) (X)
Amplitude Data register (SGAR)
15 14 D6 (R/W) (0) 13 D5 (R/W) (0) 12 D4 (R/W) (0) 11 D3 (R/W) (0) 10 D2 (R/W) (0) 9 D1 (R/W) (0) 8 D0 (R/W) (0)
Bit no.
Address : 0000F0H Read/write Default value
D7 (R/W) (0)
Decrement Grade register (SGDR)
7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X)
Bit no.
Address : 0000F3H Read/write Default value Tone Count register (SGTR)
D7 (R/W) (X)
15
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
Bit no.
Address : 0000F2H Read/write Default value
D7 (R/W) (X)
Sound Disable register (SGDBL)
7 6 () () 5 () () 4 () () 3 () () 2 () () 1 () () 0 DBL (R/W) (0)
Bit no.
Address : 0000EDH Read/write Default value
() ()
129
MB91360G Series
(2) Block Diagram
Clock input
Prescaler
S1
S0
8-bit PWM pulse generator CO EN PWM Reload
CI
Frequency counter CO EN Reload Decrement Grade register DEC
Toggle flip-flop D EN Q
1/d
Amplitude data register DEC
Decrement counter
CI CO EN
SGA
Decrement grade register
Mix
SGO
Tone pulse counter
TONE CI CO EN
Tone count register
INTE
INT
ST IRQ
130
MB91360G Series
26. STEPPER MOTOR CONTROLLER
This section provides an overview of the Stepper Motor Control Module, describe the register structure and functions, and described the operation of the Stepper Motor Control Module. The Stepping Motor Controller consists of two PWM Pulse Generators, four motor drivers, Selector Logic and the Zero Rotor Position Detector. The four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils. The combination of the PWM Pulse Generators and Selector Logic is designed to control the rotation of the motor. A Synchronization mechanism assures the synchronous operations of the two PWMs. The Zero Rotor Position Detector helps CPU obtain feed back information of the rotor movements. The following sections describe the Stepping Motor Controller 0 only. The other controllers have the same functions. The register addresses are found in the I/O map. Note : The Rotor Zero Position Detection capability is protected by a patent from Mannesmann VDO and may only be used with VDO's prior approval. (1) Block Diagram
Machine clock
Prescaler
CK PWM1 pulse generator EN PWM Selector
PWM1P0
PWM1M0
P1
P0
PWM1 compare register
PWM1 selector register
CK PWM2P0 PWM2 pulse generator CE EN PWM Load PWM2 compare register BS PWM2 select register Selector PWM2M0
Comparator Debounce logic 8-bit counter
+ - 1/9 AVCC reference voltage
PWM2M0
Zero Detect 0 register
Power down
Zero Rotor Position Detector
131
MB91360G Series
(2) Registers PWM Control 0 register (PWC0)
7 6 () () 5 P1 (R/W) (0) 4 P0 (R/W) (0) 3 CE (R/W) (0) 2 () () 1 () () 0 TST (R/W) (0)
Bit no.
Address : 0000D1H Read/write Default value Zero Detect 0 register (ZPD0)
() ()
15
14 S0 (R/W) (0)
13 TS (R/W) (0)
12 T2 (R/W) (0)
11 T1 (R/W) (0)
10 T0 (R/W) (0)
9 PD (R/W) (1)
8 RS (R/W) (0)
Bit no.
Address : 0000D0H Read/write Default value
S1 (R/W) (0)
PWM1 Compare 0 register (PWC10)
7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X)
Bit no.
Address : 0000D9H Read/write Default value
D7 (R/W) (X)
PWM2 Compare 0 register (PWC20)
15 14 D6 (R/W) (X) 13 D5 (R/W) (X) 12 D4 (R/W) (X) 11 D3 (R/W) (X) 10 D2 (R/W) (X) 9 D1 (R/W) (X) 8 D0 (R/W) (X)
Bit no.
Address : 0000D8H Read/write Default value
D7 (R/W) (X)
PWM1 Select register (PWS10)
7 6 () () 5 P2 (R/W) (0) 4 P1 (R/W) (0) 3 P0 (R/W) (0) 2 M2 (R/W) (0) 1 M1 (R/W) (0) 0 M0 (R/W) (0)
Bit no.
Address : 0000DBH Read/write Default value
() ()
PWM2 Select register (PWS20)
15 14 BS (R/W) (0) 13 P2 (R/W) (0) 12 P1 (R/W) (0) 11 P0 (R/W) (0) 10 M2 (R/W) (0) 9 M1 (R/W) (0) 8 M0 (R/W) (0)
Bit no.
Address : 0000DAH Read/write Default value
() ()
PWM Clock Disable register (SMDBL0)
7 6 () () 5 () () 4 () () 3 () () 2 () () 1 () () 0 DBL (R/W) (0)
Bit no.
Address : 0000E8H Read/write Default value
() ()
132
MB91360G Series
27. REAL TIME CLOCK
This section provides an overview of the Real Time Clock (also called Watchtimer) , describes the register structure and functions, and describes the operation of RTC module.The Real Time Clock (Watch Timer) consists of the Timer Control register, Sub-second register, Second/Minute/Hour registers, 1/2 clock divider, 21bit prescaler and Second/Minute/Hour counters. The Real Time Clock operates as the real-world timer and provides the real-world time information. (1) Block Diagram
Oscillation clock
1/2 Clock Divider
21 bit prescaler CO EN
WOT
Sub second register
UPDT
ST
Second counter CI EN LOAD CO 6 bits
Minute counter CO 6 bits
Hour counter CO 5 bits
Second/Minute/Hour register INTE0 INT0 INTE1 INT1 INTE2 INT2 INT3 INT3
IRQ
133
MB91360G Series
(2) Registers Timer disable register (WTDBL)
7 6 () () 5 () () 4 () () 3 () () 2 () () 1 () () 0 DBL (R/W) (0)
Bit no.
Address : 0000F5H Read/write Default value Timer control register (WTCR)
() ()
7
6 TST1 (R/W) (0) 14 INT3 (R/W) (0)
5 TST0 (R/W) (0) 13 INTE2 (R/W) (0)
4 () () 12 INT2 (R/W) (0)
3 RUN (R) (0) 11 INTE1 (R/W) (0)
2 UPDT (R/W) (0) 10 INT1 (R/W) (0)
1 () () 9 INTE0 (R/W) (0)
0 ST (R/W) (0) 8 INT0 (R/W) (0)
Bit no.
Address : 0000F7H Read/write Default value Address : 0000F6H Read/write Default value Sub-second register (WTBR)
TST2 (R/W) (0) 15 INTE3 (R/W) (0)
Bit no.
7
6 D6 (R/W) (X) 14 D14 (R/W) (X) 6 () ()
5 D5 (R/W) (X) 13 D13 (R/W) (X) 5 () ()
4 D4 (R/W) (X) 12 D12 (R/W) (X) 4 D20 (R/W) (X)
3 D3 (R/W) (X) 11 D11 (R/W) (X) 3 D19 (R/W) (X)
2 D2 (R/W) (X) 10 D10 (R/W) (X) 2 D18 (R/W) (X)
1 D1 (R/W) (X) 9 D9 (R/W) (X) 1 D17 (R/W) (X)
0 D0 (R/W) (X) 8 D8 (R/W) (X) 0 D16 (R/W) (X)
Bit no.
Address : 0000FBH Read/write Default value Address : 0000FAH Read/write Default value Address : 0000F9H Read/write Default value Second register (WTSR)
D7 (R/W) (X) 15 D15 (R/W) (X) 7 () ()
Bit no.
Bit no.
15
14 () ()
13 S5 (R/W) (X)
12 S4 (R/W) (X)
11 S3 (R/W) (X)
10 S2 (R/W) (X)
9 S1 (R/W) (X)
8 S0 (R/W) (X)
Bit no.
Address : 0000FEH Read/write Default value
() ()
(Continued)
134
MB91360G Series
(Continued)
Minute register (WTMR)
7 6 () () 5 M5 (R/W) (X) 4 M4 (R/W) (X) 3 M3 (R/W) (X) 2 M2 (R/W) (X) 1 M1 (R/W) (X) 0 M0 (R/W) (X)
Bit no.
Address : 0000FDH Read/write Default value Hour register (WTHR)
() ()
15
14 () ()
13 () ()
12 H4 (R/W) (X)
11 H3 (R/W) (X)
10 H2 (R/W) (X)
9 H1 (R/W) (X)
8 H0 (R/W) (X)
Bit no.
Address : 0000FCH Read/write Default value
() ()
135
MB91360G Series
28. SUBCLOCK
The Subclock System provides various power saving modes. The key of the concept is to supply the 32 kHz clock signal only to the Real Time Clock RTC) Module, while the rest of the MCU is provided with 4 MHz clock signal in order to achieve lower power supply current in the RTC32K mode. This behavior can be altered by the configuration input, SELCLK pin to switch the RTC module to operate with the 4 MHz clock. The following sections describe the operation with SELCLK connected to "0" and SELCLK connected to "1" respectively. Note : On MB91F361GA and MB91F362GA SELCLK should always be connected to "1", subclock operation is not implemented on those devices. (1) Operation of Subclock (SELCLK = 0) The next table summarizes the operation states of the components related to the Subclock System.To simplify this table SLEEP modes are not listed but the operation is the same as for RUN modes except that the CPU is stopped. Operation of components Mode Power dissipation CPU & 4 M Osc. 32 K Osc. RTC PLL Peripheral RUN RTC4M32K RTC32K STOP High Medium Low Low Lowest Run Run Stop Stop Run Run Run Stop Run Run Run Stop Run Stop Stop Stop Stop/Run Stop Stop Stop
The following table summarizes those operation modes and necessary software settings. Software Setting Mode STOP PLL1EN PLL2EN OSCD1 OSCD2 RUN RTC4M32K RTC32K STOP 0 1 1 1 0 or 1 Don't Care Don't Care Don't Care 1 1 1 Don't Care Don't Care 0 1 1 Don't Care 0 0 1
RTC32 Don't Care Don't Care 1 Don't Care
It is recommended that PLL2EN is set to "1" after the initialization to start the 32 kHz oscillation and this bit should be kept at "1" during the operation. Otherwise the 32 kHz oscillator does not start. Also bits 9 and 10 of the CLKR register (address 0046H) should always be set to "0" during operation.
136
MB91360G Series
(2) 4 MHz Real Time Clock Configuration (SELCLK = 1) When the SELCLK pad is connected logic level 1, the 32 kHz oscillation is disabled regardless of the software setting. In this configuration, the Real Time Clock Module is supplied with the 4 MHz oscillation clock signal. The following table summaries the modes available in this configuration. Operation of components Mode Power dissipation CPU & 4 M Osc. 32 K Osc. RTC Peripheral RUN RTC4M STOP High Medium Low Lowest Run Run Stop Stop Stop Stop Run Run Stop Run Stop Stop
PLL Stop/Run Stop Stop
Mode RUN RTC4M STOP
Software Setting STOP 0 1 1 PLL1EN 0 or 1 Don't Care Don't Care PLL2EN Don't Care Don't Care Don't Care OSCD1 Don't Care 0 1 OSCD2 Don't Care Don't Care Don't Care RTC32 Don't Care Don't Care Don't Care
(3) Use of Real Time Clock Module There is some additional consideration needed to operate the RTC module to achieve the desired functionality. Because the RTC module is directly connected to the 32 kHz oscillation clock, the oscillation stabilization time has to be taken care of by the software.This can be achieved by using another timer (e.g the Time Base Timer) to trigger the software to start the RTC module (Setting of ST bit to "1") . It is also important to stop the RTC module before entering the STOP mode. Otherwise, the reactivation from STOP mode results in unpredictable operation of the RTC module. After the reactivation, the oscillation stabilization time has to be measured again by the software, then the RTC module can be restarted.
137
MB91360G Series
29. 32 kHz CLOCK CALIBRATION UNIT
The 32 kHz Clock Calibration Module provides possibilities to calibrate the 32 kHz oscillation clock with respect to the 4 MHz oscillation clock. (1) Description This hardware allows the software to measure time generated by the 32 kHz clock with the 4 MHz clock. By utilizing this hardware in conjunction with software processing, the accuracy of the 32 kHz clock can come closer to that of the 4 MHz clock. The measurement result from the 32 kHz Clock Calibration Module can be processed by the software and the setting required for the Real Time Clock Module can be obtained. This module consists of two timers, one operating with the 32 kHz clock and the other operating with the 4 MHz clock. The 32 kHz timer triggers the 4 MHz timer and resulting 4 MHz timer value is stored in a register. The value stored in this register can be used for the subsequent software processing to calculate the desired Real Time Clock module's setting. (2) Block Diagram
OSC4 STRT READY RUNS OSC32 STRT CLKP RSLEEPB
UC18CLK CLK4G = OSC4 | STRT | (READY & -RUNS) ; gete
CLK4G
gete gete gete CLKPG CLK32G 32 kHz UC18TRD TIMER counter (16 bit) & anync RUN RST READY STRT 4 MHz TIMER CUTR (24 bit) UC18TRR
CLKPG2 CUTD STRTS
RUN sync RUNS 32 4
CUTR
RSLEEPB STRT SLKPG2 = CLKP | (STRT & RSLEEPB) ;
sync CLKP 32 async STRT RST STRT RB
STRT set /reset INTEN set /reset INT reset
reset & READY RUNSS1 RUNSS sync 4 CLKP
RB RSLEEP RMW UC18BUS INT RD WR RST UC18IO
RBB RSLEEPB RMWB
set READYPULSE
CUCR (3 bit) INT_I RDB WRB RSTB & INT_INT CUTR (24 bit) CUTD CU18RBI
CUTD (16 bit)
FC18
138
MB91360G Series
(3) Timing
32 kHz STRT (CLKP) STRTS (32 kHz) RUN (32 kHz) RUNS (4 MHz) 32 kHz counter (16 bit) 4 MHz counter (24 bit) READY (32 kHz) READYPULSE (CLKP) INT (CLKP)
old CUTR 0 CUTD CUTD-1 2 1 0 CUTD new CUTR
139
MB91360G Series
(4) Clocks The module operates with 3 different clocks : The 4 MHz clock OSC4, the 32 kHz clock OSC32 and the Rbus clock CLKP Synchronization circuits adapt the different domains. . All 3 clocks are gated. The 32 kHz and the 4 MHz clock are switched off if STRT is 0. CLKPG is gated by RSLEEP and CLKPG2 by RSLEEP and STRT for the 2 bits, which are set/reset by hardware. The clock frequencies have to fulfill the following requirements : 1.) Clock ratio TOSC32 > 2 x TOSC4 + 3 x TCLKP TOSC4 < 1 / 2 x TOSC32 - 3 / 2 x TCLKP TCLKP < 1 / 3 x TOSC32 - 2 / 3 x TOSC4 2.) The input frequencies must not exceed the values given in next table. Maximum operation frequencies CLKP maximum 32 MHz 31.25 ns 4 MHz OSC32 250 ns OSC4 13 MHz 76.9 ns
Examples of valid clock ratios which fulfill requirements 1 and 2 OSC32 maximum operation speed standard TDIR mode normal operation 4 MHz 500 kHz 32 kHz 250 ns 2000 ns 31.25 us 4 MHz 4 MHz OSC4 13 MHz 76.9 ns 250 ns 250 ns 4 MHz > 2 MHz CLKP 32 MHz 31.25 ns 250 ns 500 ns
140
MB91360G Series
(5) Register Description a : Calibration Unit Control Register (CUCR) Control Register low byte (CUCRL)
7 6 (R) (0) 5 (R) (0) 4 STRT (R/W) (0) 3 (R) (0) 2 (R/W) (0) 1 INT (R/W) (0) 0 INTEN (R/W) (0)
Bit no.
Address : 000191H Read/write Default value
(R) (0)
b : 32 kHz Timer Data Register (CUTD) 32 kHz Timer Data Register high byte (CUTDH)
15 14 TDD14 (R/W) (0) 13 TDD13 (R/W) (0) 12 TDD12 (R/W) (0) 11 TDD11 (R/W) (0) 10 TDD10 (R/W) (0) 9 TDD9 (R/W) (0) 8 TDD8 (R/W) (0)
Bit no.
Address : 000192H Read/write Default value
TDD15 (R/W) (1)
32 kHz Timer Data Register low byte (CUTDL)
7 6 TDD6 (R/W) (0) 5 TDD5 (R/W) (0) 4 TDD4 (R/W) (0) 3 TDD3 (R/W) (0) 2 TDD2 (R/W) (0) 1 TDD1 (R/W) (0) 0 TDD0 (R/W) (0)
Bit no.
Address : 000193H Read/write Default value
TDD7 (R/W) (0)
c : 4 MHz Timer Data Register (CUTR) 4 MHz Timer Data Register1 high byte (CUTR1H)
15 14 (R) (0) 13 (R) (0) 12 (R) (0) 11 (R) (0) 10 (R) (0) 9 (R) (0) 8 (R) (0)
Bit no.
Address : 000194H Read/write Default value
(R) (0)
4 MHz Timer Data Register1 low byte (CUTR1L)
7 6 TDR22 (R) (0) 5 TDR21 (R) (0) 4 TDR20 (R) (0) 3 TD19 (R) (0) 2 TDR18 (R) (0) 1 TDR17 (R) (0) 0 TDR16 (R) (0)
Bit no.
Address : 000195H Read/write Default value
TDR23 (R) (0)
4 MHz Timer Data Register2 high byte (CUTR2H)
15 14 TDR14 (R) (0) 13 TDR13 (R) (0) 12 TDR12 (R) (0) 11 TDR11 (R) (0) 10 TDR10 (R) (0) 9 TDR9 (R) (0) 8 TDR8 (R) (0)
Bit no.
Address : 000196H Read/write Default value
TDR15 (R) (0)
4 MHz Timer Data Register2 low byte (CUTR2L)
7 6 TDR6 (R) (0) 5 TDR5 (R) (0) 4 TDR4 (R) (0) 3 TD3 (R) (0) 2 TDR2 (R) (0) 1 TDR1 (R) (0) 0 TDR0 (R) (0)
Bit no.
Address : 000197H Read/write Default value
TDR7 (R) (0)
141
MB91360G Series
30. FLASH MEMORY
MB91360G series devices feature 512 K of embedded flash memory. On MB91F361GA it is connected to the external bus, on the other devices to the F-bus. (1) Out Line of Flash Memory The Flash Memory consists of a flash memory unit derived from the MBM29LV400C and a flash memory interface circuit. Flash Memory : * 512 Kword x 8 bit/256 Kword x 16 bit/128 Kword x 32 bit (64 Kbytex3 + 32 Kbyte + 8 Kbytex2 + 16 Kbyte) sectors * Uses automatic program algorithm (Embedded AlgorithmTM) * Erase pause/restart function * Detects completion of writing/erasing using data polling or toggle bit functions * Detects completion of writing/erasing by RY/BY pin * Compatible with JEDEC standard commands * Performs minimum of 10,000 write/erase operations * Sector erase function (any combination of sectors) * Sector protect function * Temporary sector protect cancellation function * Allows flash memory interface circuit to write to/erase flash memory both under control of external pin by writer and under control of internal bus by CPU. Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices, Inc.
142
MB91360G Series
(2) Block diagrams of Flash Memory a : Block diagram of Flash Memory Figure shows the block diagram of the flash memory unit, which has almost the same configuration as the MBM29FLV400C.
RY/BY buffer DQ0 to DQ15 RY/BY Erase circuit WE BYTE RESET Control circuit Write circuit CE OE Chip enable/ output enable circuit STB I/O buffer
Data latch
Y decoder STB Low VCC detection circuit A0 to A17 A-1 Write/erase pulse timer address latch X decoder
Y gate
cell matrix
b : Entire block diagram of Flash Memory Figure shows the entire block diagram of the Flash Memory with the flash memory interface circuit.
Flash memorry interface circuit BYTE CE OE WE A0 to A18 User Logic bus DQ0 to DQ15 RY/BY
4 Mbit flash memory BYTE CE OE WE A0 to A17 A-1 DQ0 to DQ15 RY/BY RESET
Ext.Bus I/F
External reset signal
RY/BY write enable signal
143
MB91360G Series
c : Sector configuration i) write, byte read, half word read Flash Memory mode 8 bit x 2 Sector 13 Sector 12 Sector 11 Sector 10 Sector 9 Sector 8 Sector 7 Sector 6 Sector 5 Sector4 Sector 3 Sector 2 Sector 1 Sector 0 16 KB 8 KB 8 KB 32 KB 64 KB 64 KB 64 KB 16 KB 8 KB 8 KB 32 KB 64 KB 64 KB 64 KB 7FFFFH 7C000H 7A000H 78000H 70000H 60000H 50000H 40000H 3C000H 3A000H 38000H 30000H 20000H 10000H 00000H Other modes F361GA 1FFFFF 1FC000 1FA000 1F8000 1F0000 1E0000 1D0000 1C0000 1BC000 1BA000 1B8000 1B0000 1A0000 190000 180000 Other modes other devices FFFFF FC000 FA000 F8000 F0000 E0000 D0000 C0000 BC000 BA000 B8000 B0000 A0000 90000 80000
ii) long word read MSB 8 bit x 2 Sector 13 Sector 12 Sector 11 Sector 10 Sector 9 Sector 8 Sector 7 16 KB 8 KB 8 KB 32 KB 64 KB 64 KB 64 KB LSB 8 bit x 2 Sector 6 Sector 5 Sector 4 Sector 3 Sector 2 Sector 1 Sector 0 16 KB 8 KB 8 KB 32 KB 64 KB 64 KB 64 KB Flash Memo- Other modes Other modes ry mode F361GA other devices 7FFFF 78000H 74000H 70000H 60000H 40000H 20000H 00000H 1FFFFFH 1F8000H 1F4000H 1F0000H 1E0000H 1C0000H 1A0000H 180000H FFFFF F8000 F4000 F0000 E0000 C0000 A0000 80000
144
MB91360G Series
(3) Write/Erase Modes The flash memory can be accessed in two different ways; the flash memory mode allowing write/erase directly from the external pins, and the other modes allowing write/erase from the CPU via the internal bus. These modes are selected by the external mode pins. a : Flash Memory mode The CPU stops when the mode pins are set to 111 while the INIT signal is asserted. The flash memory interface circuit is directly connected to the external bus interface, allowing direct control by the external pins. This mode makes the MCU seem like a standard flash memory at the external pins, and write/erase can be performed using a flash memory programmer. In the flash memory mode all the operations supported by the flash memory automatic algorithm can be used. b : Other modes The flash memory is located in the CS1 area of the CPU memory space and like ordinary mask ROM can be read-accessed and program-accessed from the CPU through the flash memory interface circuit. After execution of the internal Boot ROM the area for CS1 is set from 180000 to FFFFF (F361GA only) . Writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit. Therefore, this mode allows rewriting even when the MCU is soldered on the target board. The sector protect operations can not be performed in these modes. c : Control signals of flash memory Next table lists the flash memory control signals in the flash memory mode. There is almost a one-to-one correspondence between the flash memory control signals and the external pins of the MBM29LV400C. The VID (12 V) pins required by the sector protect operations are MD0, MD1 and MD2 instead of A9, RESET and OE for the MBM29LV400C. In the flash memory mode, the width of the external data bus can be 8 or 16 bit.
145
MB91360G Series
Flash Control Signals MB91F361GA/MB91F362GA Pin number 1 to 8 9 10 to 24 27 to 30 32 33 35 36 37 111 112 113 115 201 to 208 Normal function D24 to D31 A0 A1 to A15 A16 to A18 CS4 CS5 RDY BGRNT BRQ MD0 MD1 MD2 INIT D16 to D23 Flash Memory mode D24 to D31 A0 A1 to A15 A16 to A18 CS4 CS5 RDY BGRNT BRQ VDA9 VDRS VDOE INIT D16 to D23 MBM29LV400C DQ8 to DQ15 A-1 A0 to A14 A15 to A17 WE BYTE OE CE RY/BY A9 (VID) RESET (VID) OE (VID) RESET DQ0 to DQ7
A19, A20 should be pulled up, INIT must be low during power on for at least 500 ns.
146
MB91360G Series
MB91FV360GA Pin number 202 310 201 357 257 144 309 256 200 356 308 92 44 255 143 199 307 91 142 140 196 89 305 139 88 293 31 239 30 46 95 1 148 205 Normal function A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 CS4 CS5 CS6 RDY BGRNT BRQ MD0 MD1 MD2 INIT D16 D17 D18 D19 D20 Flash Memory mode A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 CS4 CS5 TMOD RDY BGRNT BRQ VDA9 VDRS VDOE INIT D16 D17 D18 D19 D20
MBM29LV400C A-1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 WE BYTE OE CE RY/BY A9 (VID) RESET (VID) OE (VID) RESET DQ0 DQ1 DQ2 DQ3 DQ4
(Continued)
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MB91360G Series
(Continued)
MB91FV360GA Pin number 45 94 260 312 204 147 93 259 203 146 258 Normal function D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Flash Memory mode D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 MBM29LV400C DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
148
MB91360G Series
(4) Flash Control Status Register (FMCS) Flash Memory Macros used in devices : Normal Flash Macro used in : MB91F361GA, MB91F362GA Fast Flash Macro used in : MB91FV360GA address FV360GA, F362GA : 00007000H F361GA : 00100180H access initial value value after Boot ROM * : It is not allowed to use RDYEG.
bit 7 FACCEN bit 6 R/W 1 1 bit 5 R/W 1 1 bit 4 RDYEG* bit 3 RDY bit 2 RDYI bit 1 WE bit 0 LPM
R/W 1 0
R 0 0
R X X
R/W 0 0
R/W 0 0
R/W 0 0
149
MB91360G Series
(5) Read/Write Access In the flash memory mode, read/write access to the flash memory must be under control of the external pins. However, with the CPU access, there are no special timing constraints on read/write access because the flash memory is controlled by the flash memory interface circuit. In this section, "write access" does not directly mean "program flash memory". It implies "activation of the flash commands". a : Read/write access in flash memory mode Next table gives the setting of pins for read/write access in the Flash Memory mode. There is no special problem with control of these pins if connected to a flash memory writer. However, in other cases, timing specifications must be met. Setting Conditions of Pins for Read/Write Access in Flash Memory Mode Operations Read Write Output disable Standby Hardware reset BGRNTX (CE) L L L H x RDY (OE) L H H x x CS4X (WE) H L H x x A0 to A18 Read address Write address x x x D16 to D31 DOUT DIN High-Z High-Z High-Z INIT H H H H L
b : Read/write access with CPU on F361GA The access timing to the flash memory unit is controlled by the flash memory interface circuit. Depending on the setting for CLKT the read operation can be completed in two or more cycles of CLKT. External Bus clear Wait cycles 32 MHz 24 MHz 16 MHz 1 1 0
c : Read access with CPU on other devices Flash Wait Control Register (FMWT) * address 00007004H access initial value value after Boot ROM Normal Flash Macro value after Boot ROM Fast Flash Macro
bit 7 bit 6 R/W 0 0 0 bit 5 FAC1 R/W 0 0 0 bit 4 FAC0 R/W 0 0 1 bit 3 EQINH R/W 0 0 0 bit 2 WTC2 R/W 0 0 0 bit 1 WTC1 R/W 1 1 1 bit 0 WTC0 R/W 1 1 1
* : FMWT register is not available on MB91F361GA (Flash on external bus)
150
MB91360G Series
Normal Flash Macro : Recommended settings Without applying clock modulation CLKB unmodulated core clock frequency [MHz] 64 48 40 32 24 16 FAC1 0 0 0 0 0 0 FAC0 1 1 1 0 0 0 EQINH 0 0 0 0 0 0 WTC2 0 0 0 0 0 0 WTC1 1 1 1 1 0 0 WTC0 1 1 0 0 1 1 FACC low cycles/wait cycles 1/3 1/3 1/2 0.5 / 2 0.5 / 1 0.5 / 1 FMWT 13H 13H 12H 02H 01H 01H
When applying clock modulation CLKB core clock frequency [MHz] 48 32 24 24 16 Peak Max. frequency 64 48 40 32 24 FAC1 0 0 0 0 0 FAC0 EQINH WTC2 WTC1 WTC0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 FACC low cycles/wait cycles 1/3 1/3 1/2 0.5 / 2 0.5 / 1 FMWT 13H 13H 12H 02H 01H
Example for flash memory read access with 1 cycle for the low time of FACC and 3 wait cycles
1 cycle FACC = "L"
3 wait cycles
CLKB
core clock F-bus address F-bus wait tFP tFACC FACC for flash F-bus data
FA
A1
A2
A3
FWAITR
FACC
FD
D1
The minimum value for tFP is 15 ns, for tFACC it is 40 ns.
151
MB91360G Series
Fast Flash Macro : Recommended settings Without applying clock modulation CLKB unmodulated core clock frequency [MHz] 64 48 40 32 24 16 FAC1 0 0 0 0 0 0 FAC0 1 0 0 0 0 0 EQINH 0 0 0 1 0 0 WTC2 0 0 0 0 0 0 WTC1 1 1 1 0 0 0 WTC0 1 0 0 1 1 1 ATDIN high cycles/wait cycles 1/3 0.5 / 2 0.5 / 2 0.5 / 1 0.5 / 1 0.5 / 1 FMWT 13H 02H 02H 09H 01H 01H
When applying clock modulation CLKB core clock Peak Max. frequency frequency [MHz] 48 32 24 24 16 64 48 40 32 24 FAC1 0 0 0 0 0 FAC0 1 0 0 0 0 EQINH 0 0 0 1 0 WTC2 0 0 0 0 0 WTC1 1 1 1 0 0 WTC0 1 0 0 1 1 ATDIN high cycles/wait cycles 1/3 0.5 / 2 0.5 / 2 0.5 / 1 0.5 / 1 FMWT 13H 02H 12H 09H 01H
Example for flash memory read access with 1 cycle for the high time of ATDIN and 3 wait cycles
1 cycle ATDIN ="H"
3 wait cycles
CLKB FA FWAITR ATDIN EQIN FD
tACC tRC A1 A2
core clock F-bus A3 address F-bus wait ATDIN for flash EQIN for flash D1 F-bus data
tWATD tWEQ
The minimum value for tWATD is 10 ns, the minimum value for tWEQ is 20 ns. The minimum value for tRC is 40 ns. The maximum value for tACC is tWATD + tWEQ + 5 ns. 152
MB91360G Series
d : Write access with CPU on other devices Recommended settings for WTC2 to WTC0 for write access to the flash memory, FACCEN of FMCS should be set to 1 for writing, so FAC1, FAC0, EQINH register settings then have no meaning for the write operation Without applying clock modulation CLKB unmodulated core clock frequency [MHz] 64 48 40 32 24 16 1 1 0 0 0 0 0 1 1 0 WTC2 WTC1 WTC0 Wait cycles FMWT
setting not allowed for writing 0 0 0 0 1 4 4 2 2 1 X4H X4H X2H X2H X1H
When applying clock modulation CLKB core clock frequency [MHz] 48 32 24 24 16 Peak Max. frequency 64 48 40 32 24 1 1 0 0 WTC2 WTC1 WTC0 Wait cycles FMWT
setting not allowed for writing 0 0 1 1 0 0 0 0 4 4 2 2 X4H X4H X2H X2H
153
MB91360G Series
(6) Automatic Write/Erase Irrespective of the Flash Memory mode or other modes, writing to/erasing the flash memory unit is performed by starting the flash memory automatic algorithm. To start the automatic algorithm, various sequences of write accesses are executed in 1 to 6 cycles. They are called Flash commands. a : Flash Commands There are four commands for starting the automatic algorithm of the Flash Memory unit; Read/Reset, Write, Chip Erase, and Sector Erase. There are also Erase Suspend and Erase Resume commands for the sector erase operation. Next tables give the command sequence lists in the flash memory and other modes. b : Command sequence Command Sequence List (CPU access) Second Fourth Read/ Third Write Fifth Write Sixth Write Write First Write Write Cycle Write Cycle Cycle of Bus Cycle of Bus Cycle of Bus Cycle of Bus Command Cycle of Bus of Bus Sequence of AdAdAdAdAdAdBus Data Data Data Data Data Data dress dress dress dress dress dress Read/ Reset*1 Read/ Reset*1 Write Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume 1 4 4 6 6
*2xxxx
xxF0

RA
RD

*25554 xxAA *2aaa8 *25554 xxAA *2aaa8 *25554 xxAA *2aaa8 *25554 xxAA *2aaa8
xx55 *25554 xxF0 xx55 *25554 xxA0
PA PD (even) (word)
xx55 *25554 xx80 *25554 xxAA *2aaa8 xx55 *25554 xx10 xx55 *25554 xx80 *25554 xxAA *2aaa8 xx55
SA (even)
xx30
Input of address *2xxxx or data (xxB0H) suspends sector erasing. Input of address *2xxxx or data (xx30H) suspends and resumes sector erasing.
Addresses in the table are the values in the CPU memory space. All addresses and data are hexadecimal values, where x is any value and *2 may be 08 to 0F on F362GA/FV360GA, 18 to 1F on F361GA. *1 : Read/Reset command reset Flash memory to read mode.
154
MB91360G Series
Command Sequence List (Flash Memory Mode) Second Fourth Read/ Third Write Fifth Write Sixth Write Write First Write Write Cycle Write Cycle Cycle of Bus Cycle of Bus Cycle of Bus Cycle of Bus Command Cycle of Bus of Bus Sequence of AdAdAdAdAdAdBus Data Data Data Data Data Data dress dress dress dress dress dress Read/ Reset* Read/ Reset* Write Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume 1 4 4 6 6
*xxxx
F0 AA AA AA AA
*5554 *5554 *5554 *5554
55 55 55 55
*aaaa
*aaaa *aaaa
F0 A0 80 80
RA
RD
*5554 *5554
55 55

*aaaa
10 30
*aaaa
*aaaa *aaaa
PA PD (even) (word)
*aaaa AA AA
*aaaa
*aaaa
*aaaa
SA (even)
Input of address *xxxx or data (B0H) suspends sector erasing. Input of address *xxxx or data (30H) suspends and resumes sector erasing.
Addresses in the table are values for writer addresses. All addresses and data are hexadecimal values, where x is any value and * may be 0 to 7. RA : Read address PA : Write address. Only even addresses can be specified. SA : Sector address (See next table) . Only even addresses can be specified. RD : Read data PD : Write data. Only word data can be specified.
155
MB91360G Series
Sector Address for half word mode Sector SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 A18 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A17 1 1 1 1 1 0 0 1 1 1 1 1 0 0 A16 1 1 1 1 0 1 0 1 1 1 1 0 1 0 A15 1 1 1 0 1 1 1 0 A14 1 0 0 1 0 0 A13 1 0 1 0 Address range 7C000H to 7FFFFH 7A000H to 7BFFFH 78000H to 79FFF 70000H to 77FFFH 60000H to 6FFFFH 50000H to 5FFFFH 40000H to 4FFFFH 3C000H to 3FFFFH 3A000H to 3BFFFH 38000H to 39FFFH 30000H to 37FFFH 20000H to 2FFFFH 10000H to 1FFFFH 00000H to 0FFFFH
156
MB91360G Series
(7) Connection to Flash Memory The Flash Memory mode of the MB91F361GA is intended mainly for external connection to a flash memory writer. As indicated in Table Flash Control Signals, there is a slight difference between the external pins of the MB91F361GA and the MBM29LV400C (4 Mbit flash memory) . Connection to an MBM29LV400C writer requires the socket adapter.
Socket adapter flash writer A9 2.2 k RESET 2.2 k OE 2.2 k MD0 2.2 k MD1 2.2 k MD2 2.2 k RDY INIT MB91F361GA A10
157
MB91360G Series
(8) Notes to Use of Flash Memory Notes on the Flash Memory in MB91360G series devices are given below. a : Input of hardware reset (INIT) To input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum of 500 ns should be taken at a low-level width. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in progress, a minimum of 50 ns should be taken in a low-level width. In this case, 20 s are required until data can be read after the executing operation has been terminated to initialize the flash memory. A hardware reset during writing undefined data being written. A hardware reset during erasing may make the sector being erased unusable. b : Canceling software reset, watchdog timer reset, and hardware standby When writing/erasing the flash memory with the CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run away. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions should be inhibited during writing/erasing the Flash Memory. c : Program access to Flash Memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to the internal ROM mode, writing/erasing should be started after switching the program area to another area such as RAM. In this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed. For the same reason, all interrupt sources should be disabled while the automatic algorithm is operating. d : Hold function When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed and many cause erroneous writing/erasing. When the acceptance of a hold request is enabled, ensure that the WE bit of the control status register (FMCS) is 0. e : Applying VID Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on.
158
MB91360G Series
(9) Timing Diagrams in Flash Mode Each timing diagram for the external pins of the MB91F361 in the Flash Memory mode is shown below. a : Data read by read access
tRC
A18 to A0
tAC 120 ns
Address stable
BGRNT (CE)
tOE 50 ns
30 ns
tDF
RDY (OE)
120 ns (TOGGLE) 0 ms (Read) tOEH
CS4 (WE)
tCE 120 ns High-Z Output defined
tOH 0 High-Z
D31 to D16
b : Write Data polling Read (WE control)
Third bus cycle Data Polling PA tAS tAH PA tRC
A18 to A0
7AAAAH tWC
BGRNT (CE)
tGHEL
RDY (OE)
tWP tWHWH1
CS4 (WE)
tCS A0H tDS tWPH tDH tOE tDF PD D23 DOUT tOH tCE
D31 to D16 VDD (= 5.0 V)
PA : Write address PD : Write data D23 : Reverse output of write data DOUT : Output of write data Note : The last two bus cycle sequences out of the four are described.
159
MB91360G Series
c : Write Data polling Read (CE control)
Third bus cycle Data Polling PA tAS tWH tAH PA
A18 to A0
7AAAAH tWC
BGRNT (CE)
tGHEL
RDY (OE)
tCP tWHWH1
CS4 (WE)
tWS A0H tDS tCPH tDH
D31 to D16 VDD (= 5.0 V)
PD
D23
DOUT
PA : Write address PD : Write data D23 : Reverse output of write data DOUT : Output of write data Note : The last two bus cycle sequences out of the four are described. d : Chip erase/sector erase command sequence
tAS tAH 75554H 7AAAAH 7AAAAH 75554H SA*
A18 to A0
7AAAAH
BGRNT (CE)
tGHWL
RDY (OE)
tWP
CS4 (WE)
tCS
tWPH tDH AAH tDS 55H 80H AAH 55H 10H/30H
D31 to D16
VDD
tVCS
Note : SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing. 160
MB91360G Series
e : Data polling
tCH
BGRNT (CE)
tOE tDF
RDY (OE)
tOEH
CS4 (WE)
tCE * D23 tWHWH1 or tWHWH2 D23
tOH D23 = Valid data High-Z
D31 to D16
D31 - D16 = Invalid tEOE
D31 - D16 =
Valid data
* : DQ7 is valid data (The device terminates automatic operation) . f : Toggle bit
BGRNT (CE)
tOEH
RDY (OE)
tOES
CS4 (WE)
D22 = Toggle D22 = Toggle * * D22 = Stop toggling D31 to D16 = Valid
Data (D31 to D16)
tOE
* : DQ6 stops toggling (The device terminates automatic operation) .
g : RY/BY timing during writing/erasing
BGRNT (CE)
Rising edge of last write pulse
RDY (OE)
Writing or erasing
CS4 (WE)
tBUSY
161
MB91360G Series
h : INIT and RY/BY timing
BGRNT (CE)
CS4 (OE)
tRP
BRQ (RY/BY)
tREADY
i : Enable sector protect/verify sector protect
A18 to A13 A7, A2, and A1 12 V 5V 12 V 5V
tVLHT
SAx
SAy
(A7, A2, A1) = (0, 1, 0)
MD0 (A9(VID))
MD2 (OE(VID))
tVLHT
CS4 (WE)
RDY (OE)
tOESP
tWPP
D31 to D16
tCSP
01H tOE
SAx : First sector address SAy : Next sector address
162
MB91360G Series
j : Temporary sector protect cancellation
MD1 (RESET (VID)) BGRNT (CE)
12 V 5V
5V
CS4 (WE)
tVLHT Write/erase command sequence
BRQ (RY/BY)
Sector protect cancellation
163
MB91360G Series
(10) AC Characteristics in Flash Memory Mode The AC specifications for the external pins of the MB91F361 in the Flash Memory mode are shown below. They apply to the case where the user performs read/write access in the Flash Memory mode. They are not needed for access in the normal mode and for use of a flash memory writer. The values are subject to change without prior notice. a : Read access AC Characteristics for Read Access (Under recommended conditions) Parameter Read cycle time Address access time CE to data output OE to data output CE to output floating OE to output floating Previous cycle data output hold time INITI pin to return to read mode Symbol tRC tACC tCE tOE tDF tDF tOH tReady Test Conditions CE = VIL OE = VIL OE = VIL Value Min. 120 0 Typ. Max. 120 120 50 30 30 20 Unit ns ns ns ns ns ns ns s
164
MB91360G Series
b : Write [write/erase command] access (WE control) AC Characteristics for Write Access (WE Control) (Under recommended conditions) Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time Read Toggle and data polling Symbol tWC tAS tAH tDS tDH tOES tOEH tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS
2
Value Min. 120 0 50 50 0 0 0 10 0 0 0 50 20 50 4 100 4 4 500 50 Typ. 16 1.5 Max. 30
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s ns ns
Read recovery time before write CE setup time CE hold time Write pulse width Write pulse width High level Write continuation time Sector erase continuation time*1 VCC setup time Voltage transition time* Write pulse width*2 OE setup time for validating WE*2 CE setup time for validating WE* INIT pulse width RY/BY delay until write/erase is enabled
2
tVLHL tWPP tOESP tCSP tRP tBUSY
*1 : The internal preprogramming time before erasing is not included. *2 : Applies only to sector protection
165
MB91360G Series
c : Write [write/erase command] access (CE control) AC Characteristics for Write Access (CE Control) (Under recommended conditions) Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time Read Toggle and data polling Symbol tWC tAS tAH tDS tDH tOES tOEH tGHWL tWS tWH tCP tCPH tWHWH1 tWHWH2 tVCS tRP tBUSY Value Min. 120 0 50 50 0 0 0 10 0 0 0 50 20 50 500 50 Typ. 16 1.5 Max. 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns
Read recovery time before write WE setup time WE hold time CE pulse width CE pulse width High level Write continuation time Sector erase continuation time* VCC setup time INIT pulse width RY/BY delay until write/erase is enabled
* : The internal preprogramming time before erasing is not included.
166
MB91360G Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Digital supply voltage Stepper motor control supply voltage Storage temperature Power consumption Digital input voltage Analog input voltage Analog supply voltage Analog reference voltage Static DC current into digital I/O Symbol VDD-VSS HVDD-HVSS Tstg PTOT VIDIG VIA VDDA-VSSA VREFH/L-VSSA II/ODC Rating Min. -0.3 -0.3 -55 -0.3*2 -0.3 -0.3 -0.3 -2 Max. 6.0 6.5 +125 *1 5.8 5.8 5.8 5.8 2 Unit V V C mW V V V V mA TA = +25C VSS = 0 V, VDD = 5 V VSSA = 0 V, VDDA = 5 V VSSA = 0 V VSSA = 0 V II/ODC < ISRUN Condition
*1 : The value differs in each kind of the product. *2 : Making full use of the allowed static DC correct into digital I/O will lead to lower values for VIDIG Min. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Parameter Operating temperature Digital supply Supply voltage Stepper motor (Internal voltage control supply regulator) Analog supply RAM data retention voltage Symbol TA VDD - VSS HVDD - HVSS VDDA - VSSA VDD - VSS Value Min. -40 4.25* 4.75 4.9 3.0 5 5 5 Typ. Max. +85 5.25 5.25 5.1 Unit C V V V V VDDCORE = 3.3 V HVSS = 0 V VSSA = 0 V Condition
*: This is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at voltages less or equal than 4.5 V (see "s PERIPHERAL RESOURCES 23. POWER DOWN RESET") . WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
167
MB91360G Series
3. DC Characteristics
Parameter Run mode Current consumption RTC mode Stop mode Symbol Isrun IsRTC Isstop VOHH VOHL H-port output voltage Stepper motor control SMC comparator threshold voltage Slew rate OverThreshold voltage voltage UnderAlarm comvoltage parator Switching hysteresis Alarm sense time Input resistance Threshold voltage Power down Reset Switching hysteresis Reset sense time Digital out- Output "H" voltage puts Output "L" voltage VOHH VOHL VOHH VOHL VTHcomp VTAH VTAL V TAHYS tAS Rin VTPOR VTPORHYS
4
Value Min. HVDD - 500 HVSS + 125 HVDD - 500 HVSS + 125 HVDD - 500 HVSS + 125 HVDD / 9 - 70
/5 VDDA - 5% /5 VDDA - 5%
4
Typ. 0.5 10 HVDD / 9 40
/5 VDDA /5 VDDA
4
Max. *1 1.25 500 200
Unit
Condition
mA TA = 25 C mA fclk = 4 MHz at TA = 25 C A fclk = 32 kHz at TA = 25 C A fclk = 0 at TA = 25 C
HVDD - 125 mV Iol = 30 mA, TC = 25 C HVSS + 500 mV Iol = 30 mA, TC = 25 C HVDD - 125 mV Iol = 27 mA, TC = 85 C HVSS + 500 mV Iol = 27 mA, TC = 85 C HVDD - 125 mV Iol = 30 mA, TC = -40 C HVSS + 500 mV Iol = 30 mA, TC = -40 C HVDD / 9 + 70
/5 VDDA + 5% /5 VDDA + 5%
mV ns V V mV s M at VTAH, VTAL V mV s V V Iload = 4mA Iload = -4mA Cload = 0 pF (external 4 : 1 divider)
2
2
2
12.5 5 3.5 20 VDD - 0.5 VSS
25 4.0 50
50 10 4.5 80 10 VDD VSS + 0.4
tRS VOH VOL
*1 : See "4. Run Mode Current/Power Consumption".
(Continued)
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MB91360G Series
Value Min. 0.65 x VDD VSS 0.8 x VDD VSS 0.8 x VDD VSS 0.65 x VDD VSS 0.65 x VDD VSS -1 Typ. 0.5 50 10 Max. VDD 0.25 x VDD VDD 0.2 x VDD VDD 0.5 x VDD 0.6 x VDD VDD 0.25 x VDD VDD 0.25 x VDD 16 +1
Parameter High voltage CMOS range (Type : Q, S, Low voltage Y, T) range CMOS SchmittTrigger (Types : E, F, U) CMOS Automotive SchmittTrigger (Types : A, B, K1, M1, J) High voltage range Low voltage range High voltage range Low voltage range hysteresis voltage
Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL CIN IIL Rup1 Rup2
Unit V V V V V V V V V V V V pF
Condition
VDDmin = 4.25 V VDDmin = 4.75 V
Digital Inputs*2
High voltage CMOS 3/5 V range (Type : L, N, Low voltage O) range High voltage range Low voltage range CMOS 3 V Input capaci(Type : P, W) tance Input leakage current Pull up resistor
A TA = 25 C k Types : E, U k Type : S (Continued)
*2 : valid for bidirectional tristate I/O PAD cell
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MB91360G Series
(Continued)
Parameter Reference voltage input Input voltage range ADC inputs Input resistance Input capacitance Input leakage current Impedance of external output driving the ADC input DAC analog outputs Output voltage Output impedance Output capacitance Symbol VREFH VREFL Vimax Vimin RI CI IIL Vout Rout Cout VoutHIGH VoutLOW Iout VoutHIGH VoutLOW Iout VoutHIGH VoutLOW VoutHIGH VoutLOW Iout Vsurge Value Min. VREFL + 3 VSSA VREFL -5 VSSA VDD - 0.5 VSS 4 VDD - 0.5 VSS 4 VDD - 0.8 VSS 3 2 Typ. 2.9 0.1 Max. VDDA VREFH - 3 VREFH 3.6 30 5 4.0 VDDA 20 VDD VSS + 0.4 VDD VSS + 0.4 VSS + 0.8 VDD VSS + 0.4 1 Unit V V V V k pF A k V k pF V V mA V V mA V V V V mA IoutLOW = 3 mA ms Rdischarge = 1.5 k Cdischarge = 100 pF IoutHIGH = 14 mA IoutLOW = 24 mA external voltage follower required TA = 25 C at sampling time of 1.6 s Condition
Output voltage Sound generator Output current PPG Output voltage Output current LED I2C Bus Interface (Open Drain Output) Output voltage Output voltage Output current
Lock-up time PLL1 (4 MHz 16 MHz to 64 MHz) ESD Protection (Human body model MIL883-B compliant)
kV
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MB91360G Series
4. Run Mode Current/Power Consumption
The power dissipation during normal operation is determined by the total power dissipation of the internal logic PC, the dissipation from analog modules PA and the power dissipation PIO of the I/O buffers. Among the I/O buffers the dissipation caused by the stepper motor drivers PSMC should be taken into special consideration. So the overall power consumption PD will be calculated as a sum of Pc + PA + PSMC + PIO . (1) Logic Power Consumption The following formula can be used to calculate the maximum core current consumption when the PLL is used depending on the frequency settings for the internal clocks : ICC = 3.45 [mA/MHz] x CLKB [MHz] + 2.52 [mA/MHz] x CLKP[MHz] + 0.72 [mA/MHz] x CLKT [MHz] + 35.5 mA. If clock modulation is used the following value must be added to this result : 0.24 [mA/MHz] x CLKB [MHz]. This results in the following values (higher clock settings are not allowed) : Clock frequencies [MHz] Maximum Core Logic Power Current Consumption CLKB CLKP CLKT Consumption [mA] PC at 5.25 V [mW] 64 48 48 32 32 24 24 16 2 0.125 16 24 16 32 16 24 12 16 2 0.125 16 24 16 32 16 24 12 16 2 0.125 308 290 264 257 205 202 163 146 40 30 1.70 1.52 1.40 1.35 1.08 1.06 0.86 0.77 0.21 0.16 no PLL, no clock modulation no PLL, no clock modulation
Remarks no clock modulation possible
In addition to this power consumption of the MCU core logic the following contributions to the overall power consumption have to be considered : (2) Analog Power Consumption Module DAC ADC Power down reset Maximum Current Consumption 1 mA / channel 7 mA 0.5 mA Remarks
Alarm Comparator 0.5 mA To calculate the analog power consumption PA, the current contributions of the active modules have to be multiplied by the maximum analog supply voltage of 5.1 V.
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MB91360G Series
(3) I/O and SMC Power Consumption SMC drivers : The average current consumption per SMC channel is 38.2 mA, for four channels this results in 152.8 mA. At 2 x 0.5 V this results in 153 mW power consumption PSMC for four channels of stepper motor drivers. Other I/O Buffers : The power dissipation (PIO) (at 5.25 V) of the I/O buffers is represented as the sum of the dynamic power dissipation (PAC) and the static power consumption (PDC) . PIO = PAC x 1.1 + PDC The following table lists values for PAC : Buffer Type Normal Input Bidirectional Input 4 mA Bidirectional Output 4 mA Output 8 mA Bidirectional Output
Power Consumption 12.4 194 + 25 CL
Unit
W/MHz @ 5.0 V
353 + 25 CL 8 mA Output PAC = PIB x In x f x operating rate + POB x On x f x operating rate PIB : POB : In : On : f: Power Consumption of Input Buffers and Bidirectional Inputs Power Consumption of Output Buffers and Bidirectional Outputs Total number of input buffers and bidirectional buffer inputs Total number of output buffers and bidirectional buffer outputs System frequency
Operating rate : 1.0 if all buffers are switched simultaneously at system frequency PDC is the caused by off chip loads which are drawing static currents. PDC = VO x IO x DCN VO : Output voltage drop - usually 0.4 V IO : Output current - usually 4 mA DCN : Number of output buffers and bidirectional buffers driving off chip loads causing static currents.
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MB91360G Series
5. Clock Settings
Max. frequency setting 64 MHz 32 MHz Resource bus Ext. Bus Clock for CAN CLKP CLKT CANCLK 32 MHz 32 MHz 32 MHz
Clock domain
Clock name
Remark under normal operating conditions (see "4. Run Mode Current/Power Consumption") * for supply voltage between 4.25 and 3.5 V
Core
CLKB
* : F361GA : If the maximum frequency of 64 MHz is set for CLKB, it is not allowed to have an odd division factor for CLKT. F362GA : If the maximum frequency of 64 MHz is set for CLKB and an odd division factor for CLKT (3, 5, 7, 9, 11, 13, 15) has been selected, then the option to create an asymmetrical CLKT must be used (set bit 14 of the F362MD register to "1") .
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MB91360G Series
6. Converter Characteristics
* A/D Converter Parameter Resolution Conversion error Non-linearity Differential Non-linearity Zero Reading voltage Full scale reading voltage Input current Reference voltage current * D/A Converter Parameter Resolution Differential linearity error Symbol Value Min. -0.9 Typ. Max. 10 +0.9 Unit Bit Bit Remark Symbol V0T VFST IA@VDDA IR Value Min. AVRL - 3.5 AVRH - 5.5 Typ. AVRL + 0.5 AVRH - 1.5 3.0 1.6 Max. 10 5.0 2.5 1.9 AVRL + 4.5 AVRH + 2.5 7.0 2.6 Unit Bit LSB LSB LSB LSB LSB mA mA overall error Remark
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MB91360G Series
7. A/D Converter Glossary
* Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000 0000" "00 0000 0001") to the full-scale transition point (between "11 1111 1110" "11 1111 1111") . * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. * Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF 1.5 LSB' 3FE 3FD {1 LSB' x (N - 1) + 0.5 LSB'} Digital output Actual conversion characteristic
004 003 002 Ideal characteristic 001 0.5 LSB' AVRL Analog input AVRH VNT (measured value) Actual conversion
Total error of digital output N
VNT - {1 LSB' x (N - 1) + 0.5 LSB'} [LSB] 1 LSB' VOT ' (Ideal value) = AVRL + 0.5 LSB' [V]
=
VFST ' (Ideal value) = AVRH - 1.5 LSB' [V] VNT : A voltage for causing transition of digital output from (N - 1) to N
(Continued)
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MB91360G Series
(Continued)
Linearity error
3FF 3FE {1 LSB x (N - 1) + VOT} 3FD VFST (measured value) 004 003 002 Ideal characteristic 001 VOT (measured value) AVRL Analog input AVRH AVRL N-2 VNT (measured value) Actual conversion characteristic N Actual conversion characteristic N+1
Differential linearity error
Ideal characteristic
Actual conversion characteristic
Digital output
Digital output
N-1
V(N + 1)T (measured value) VNT (measured value) Actual conversion characteristic AVRH
Analog input
Linearity error of digital output N
=
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB -1 [LSB]
[LSB]
Differential linearity error of digital output N = 1 LSB = VFST - VOT 1022 [V]
1 LSB' (ideal value) =
AVRH - AVRL 1022
[V]
VOT : A voltage for causing transition of digital output from (000) H to (001) H VFST : A voltage for causing transition of digital output from (3FE) H to (3FF) H VNT : A voltage for causing transition of digital output from (N - 1) H to N
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MB91360G Series
8. Notes on Using A/D Converter
Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 4 k. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. * Analog input Equivalent Circuit
Analog input pin Comparator RO C0 RON : 3.6 K C0 : 30 pF
* Error As the absolute value of AVRH decreases, relative error increases.
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MB91360G Series
9. The Time for Power Supply
Parameter Power supply raising slope Power supply raising slope Symbol V/t tR Value Min. 80 Typ. Max. 0.05 Unit V/s s
4.2 V
VDD
0.2 V t
V
10. AC Characteristics
* Measurement conditions Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Load conditions Symbol VIH VIL VOH VOL VIH VIL VOH VOL Value according to I/O spec 0.5 x VDD 0.5 x VDD 3.0 0 0.5 x VDD 0.5 x VDD Unit V V V V V V V V VDD = 3.0 to 3.6 V, TA = -40 to +85 C VDD = 4.25 to 5.25 V, TA = -40 to +85 C Conditions
Output pin C = 50 pF
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MB91360G Series
* External bus clock
(VDD = 4.25 V to 5.25 V, TA = -40 C to +85 C) Symbol tCYC tCHCL tCLCH Pin name CLK CLK CLK Value Min. tCPT tCYC / 2 - 10 tCYC / 2 - 10 Max. tCYC / 2 + 10 tCYC / 2 + 10 Unit ns ns ns
Signal CLK cycle CLK rise CLK fall CLK fall CLK rise
Note : This is only valid for operation without clock modulator
tCYC tCHCL tCLCH
VOH
VOH VOL
CLK
The values for tCHCL and tCLCH are heavily dependent on the load connected to the CLK pin. The following diagrams show this dependency for the worst case situation. The first diagram shows the situation for even division ratios between CLKB and CLKT, the second diagram shows this for odd division ratios between CLKB and CLKT (ASYMCLKT bit is not set) . It has to note that when the combination of CLK frequency and load at CLK pin is such that rise or fall times are longer than tCYC / 2 the duty ratio can get worse.
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MB91360G Series
Even CLKB/CLKT division ratios : deviation of tCHCL from tCYC / 2 versus load
14,0 12,0 10,0 8,0 ns 6,0 4,0 2,0 0,0 0 20 40 60 pF 80 100 120 5V 3.3 V
Odd CLKB/CLKT division ratios : deviation of tCHCL from tCYC / 2 versus load
14,0 12,0 10,0 8,0 ns 6,0 4,0 2,0 0,0 0 20 40 60 pF 80 100 120 5V 3.3 V
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MB91360G Series
* External bus interface
(VDD = 4.25 V to 5.25 V, TA = -40 C to +85 C) Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX tCHASL tCHASH AS AS RD D31 to D0 Pin name CLK CS6 to CS0 CLK A20 to A0 CLK D31 to D0 CLK RD CLK WR3 to WR0 A20 to A0 D31 to D0 Value Min. 25 0 Max. 15 15 20 16 15 15 15 15 3 / 2 x tCYC - 30 tCYC - 20 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Signal CS6 to CS0 delay time CS6 to CS0 delay time Address delay time Data delay time RD delay time RD delay time WR3 to WR0 delay time WR3 to WR0 delay time Effective address Effect data input time RD (fall) Effect data input time Data set up RD (rise) time RD (rise) Data hold time AS delay time AS delay time
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MB91360G Series
tCYC VOH tCHASL VOH tCHASH VOH VOH
CLK
VOL
VOL
AS
tCHCSL
VOL
tCHCSH VOH
CS0 - CS6
VOL tCHAV
A23 - A00
VOH VOL tCLRL
tCLRH VOH tRLDV
RD
VOL
tRHDX tDSRH VOH VOL VOH VOL
tAVDV
D31 - D00
tCLWL
tCLWH VOH
WR3 - WR0
VOL tCHDV
D31 - D00
VOH VOL
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MB91360G Series
* RDY
(VDD = 4.25 V to 5.25 V, TA = -40 C to +85 C) Signal Symbol tRDYS tRDYH Pin name CLK RDY CLK RDY Value Min. 16 0 Max. Unit ns ns
RDY setup RDY hold
tCYC
CLK
VOH
VOL
VOH
VOL tRDYS tRDYH
tRDYS tRDYH
RDY case 1
VIL
VIH
RDY case 2
VIH
VIL
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MB91360G Series
* BGRNT
(VDD = 4.25 V to 5.25 V, TA = -40 C to +85 C) Signal Symbol tCHBGL tCHBGH tXHAL BGRNT tHAHV tcyc - 15 tcyc + 15 ns Pin name CLK BGRNT Value Min. tcyc - 15 Max. 10 10 tcyc + 15 Unit ns ns ns
BGRNT BGRNT Bus access enabled BGRNT falling Bus access disabled BGRNT rising
tCYC VOH VOH VOH
CLK
BRQ
tCHBGL
tCHBGH
BGRNT
tXHAL
VOH tHAHV
Other Ports
High-Z
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MB91360G Series
* DMA
(VDD = 4.25 V to 5.25 V, TA = -40 C to +85 C) Signal Symbol tDRWH tDSWH tCLDL tCLDH tCLEL tCLEH Pin name DREQ0 DSTP0* CLK DACK0 CLK DEOP0 Value Min. 5tCYC 5tCYC Max. 20 20 20 20 Unit ns ns ns ns
DREQ DSTP DACK DEOP
tCYC
CLK
tCLDL tCLDH
DACK0
tCLEL
tCLEH
DEOP0
tDSWH
DSTP0
DREQ0
tDRWH
* : DSTP and DEOP share a pin. The pin is possible to change DSTP and DEOP functions using a port function register.
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MB91360G Series
s PACKAGE THERMAL RESISTANCE INFORMATION
Thermal Resistance [ C/W] Package 0 m/s FPT-208P-M04 PGA-401C-A02 16 16 Theta-ja 1 m/s 13 8.5 3 m/s 11 5.5 Theta-jc 2.5
s ORDERING INFORMATION
Part number MB91FV360GACR MB91F361GAPFVS MB91F362GAPFVS Package 401-pin Ceramic PGA (PGA-401C-A02) 208-pin Plastic QFP (FPT-208P-M04) 208-pin Plastic QFP (FPT-208P-M04) Remarks
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MB91360G Series
s PACKAGE DIMENSIONS
401-pin ceramic PGA (PGA-401C-A02)
48.26 0.55 SQ (1.900 .022)
2.54 (.100) TYP
0.40 0.10 DIA (.016 .004)
1.00 (.039) DIA TYP (4 PLCS)
45.72 (1.800) REF
INDEX AREA
1.20 0.25 (.047 .010) 3.40 0.40 (.134 .016) 5.27 (.207) MAX
1.02 (.040) C TYP (4 PLCS)
EXTRA INDEX PIN
C
1994 FUJITSU LIMITED R401002SC-2-2
Dimensions in mm (inches).
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MB91360G Series
208-pin plastic QFP (FPT-208P-M04)
Note : Pins width and pins thickness include plating thickness.
30.600.20(1.205.008)SQ 28.000.10(1.102.004)SQ
156 105
0.17 -0.08 .007 -.003
104
+0.03 +.001
157
0.08(.003)
Details of "A" part 3.75 -0.30 .148 -.012
+0.20 +.008
(Mounting height)
0.40 -0.15 INDEX 0~8
53
+0.10 +.004
.016 -.006 (Stand off)
208
"A"
LEAD No.
1
52
0.50(.020)
0.220.05 (.009.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.08(.003)
M
C
2000 FUJITSU LIMITED F208020S-c-2-3
Dimensions in mm (inches).
Note : The design may be modified changed without notice, contact to Fujitsu sales division when using the device.
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MB91360G Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0107 (c) FUJITSU LIMITED Printed in Japan

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